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nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment 

Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2021-02-09 17:44:07 +01:00 committed by Patrick Georgi
parent b53dfc727e
commit f843e0a8ef
2 changed files with 2 additions and 2 deletions
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2
src/northbridge/intel/haswell/registers/mchbar.h
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@ -13,7 +13,7 @@
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */
#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
#define EDRAMBAR 0x5408 /* Base address for eDRAM */

2
src/northbridge/intel/sandybridge/registers/mchbar.h
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@ -483,7 +483,7 @@
#define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */
#define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */
#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */