amdk8: Move to implicit length patching
Change-Id: I8b4c36adaa7ea791ae1a8f7c0d059b9201b08f94 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7332 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
a09f4db396
commit
f8457985d8
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@ -25,7 +25,7 @@
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#include <cpu/amd/powernow.h>
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/* FIXME: this should be implemented but right now all boards hardcode it. */
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int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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return 0;
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return;
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}
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@ -30,23 +30,23 @@
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#include <cpu/amd/amdk8_sysconf.h>
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#include <arch/cpu.h>
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static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
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u8 *pstate_fid, u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control)
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static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
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u8 *pstate_fid, u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control)
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{
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int lenp, lenpr, i;
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int i;
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if ((onlyBSP) && (coreID != 0)) {
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plen = 0;
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pcontrol_blk = 0;
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}
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lenpr = acpigen_write_processor(coreID, pcontrol_blk, plen);
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lenpr += acpigen_write_empty_PCT();
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lenpr += acpigen_write_name("_PSS");
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acpigen_write_processor(coreID, pcontrol_blk, plen);
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acpigen_write_empty_PCT();
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acpigen_write_name("_PSS");
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/* add later to total sum */
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lenp = acpigen_write_package(pstate_num);
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acpigen_write_package(pstate_num);
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for (i = 0;i < pstate_num;i++) {
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u32 status, c2;
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@ -56,21 +56,19 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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(pstate_vid[i] << 6) |
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pstate_fid[i];
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lenp += acpigen_write_PSS_package(pstate_feq[i],
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pstate_power[i],
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0x64,
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0x7,
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c2,
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status);
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acpigen_write_PSS_package(pstate_feq[i],
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pstate_power[i],
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0x64,
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0x7,
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c2,
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status);
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}
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/* update the package size */
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acpigen_patch_len(lenp - 1);
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acpigen_pop_len();
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lenpr += lenp;
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lenpr += acpigen_write_PPC(pstate_num);
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acpigen_write_PPC(pstate_num);
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/* patch the whole Processor token length */
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acpigen_patch_len(lenpr - 2);
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return lenpr;
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acpigen_pop_len();
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}
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#if CONFIG_K8_REV_F_SUPPORT
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@ -79,9 +77,8 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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* Two parts are included, the another is the DSDT reconstruction process
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*/
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static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int len;
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u8 processor_brand[49];
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u32 *v, control;
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struct cpuid_result cpuid1;
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@ -358,8 +355,6 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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write_pstates:
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len = 0;
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control = (0x3 << 30) | /* IRT */
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(0x2 << 28) | /* RVO */
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(0x1 << 27) | /* ExtType */
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@ -368,12 +363,10 @@ write_pstates:
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(0x5 << 11); /* VST */
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for (index = 0; index < (cmp_cap + 1); index++) {
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len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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Pstate_fid, Pstate_power, index,
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pcontrol_blk, plen, onlyBSP, control);
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}
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return len;
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}
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#else
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@ -754,13 +747,13 @@ struct cpuentry entr[] = {
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{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
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};
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static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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u8 cmp_cap;
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struct cpuentry *data = NULL;
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uint32_t control;
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int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0;
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int i = 0, index = 0, Pstate_num = 0, dev = 0;
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msr_t msr;
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u8 Pstate_fid[MAXP+1];
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u16 Pstate_feq[MAXP+1];
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@ -773,7 +766,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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cpuid1 = cpuid(0x80000007);
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if((cpuid1.edx & 0x6)!=0x6) {
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printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
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return 0;
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return;
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}
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cpuid1 = cpuid(0x80000001);
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@ -803,7 +796,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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if (data == NULL) {
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printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
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return 0;
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return;
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}
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#if CONFIG_MAX_PHYSICAL_CPUS
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@ -836,8 +829,6 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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* time = value*1uS (often seen value: 2uS)
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*/
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len = 0;
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Pstate_fid[0] = Max_fid;
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Pstate_feq[0] = fid_to_freq(Max_fid);
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Pstate_vid[0] = Max_vid;
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@ -864,28 +855,23 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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continue;
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for (i = 0; i < (cmp_cap + 1); i++) {
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len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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Pstate_fid, Pstate_power, index+i,
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pcontrol_blk, plen, onlyBSP, control);
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}
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index += i;
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}
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printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
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return len;
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}
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#endif
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int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int lens;
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char pscope[] = "\\_PR";
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lens = acpigen_write_scope(pscope);
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lens += pstates_algorithm(pcontrol_blk, plen, onlyBSP);
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//minus opcode
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acpigen_patch_len(lens - 1);
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return lens;
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acpigen_write_scope(pscope);
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pstates_algorithm(pcontrol_blk, plen, onlyBSP);
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acpigen_pop_len();
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}
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@ -20,6 +20,6 @@
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#ifndef POWERNOW_H
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#define POWERNOW_H
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int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP);
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void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP);
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#endif
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@ -96,14 +96,13 @@ void mainboard_inject_dsdt(void)
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global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE);
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if (gnvs) {
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int scopelen;
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memset(gnvs, 0, sizeof(*gnvs));
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acpi_write_gvars(gnvs);
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/* Add it to SSDT. */
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scopelen = acpigen_write_scope("\\");
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scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
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acpigen_patch_len(scopelen - 1);
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acpigen_write_scope("\\");
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acpigen_write_name_dword("NVSA", (u32) gnvs);
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acpigen_pop_len();
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}
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}
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@ -204,71 +204,65 @@ unsigned long acpi_fill_slit(unsigned long current)
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return current;
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}
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static int k8acpi_write_HT(void) {
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int len, lenp, i;
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static void k8acpi_write_HT(void) {
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int i;
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len = acpigen_write_name("HCLK");
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lenp = acpigen_write_package(HC_POSSIBLE_NUM);
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acpigen_write_name("HCLK");
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acpigen_write_package(HC_POSSIBLE_NUM);
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for(i=0;i<sysconf.hc_possible_num;i++) {
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lenp += acpigen_write_dword(sysconf.pci1234[i]);
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acpigen_write_dword(sysconf.pci1234[i]);
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}
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for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
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lenp += acpigen_write_dword(0x0);
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acpigen_write_dword(0x0);
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}
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acpigen_patch_len(lenp - 1);
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len += lenp;
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acpigen_pop_len();
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len += acpigen_write_name("HCDN");
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lenp = acpigen_write_package(HC_POSSIBLE_NUM);
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acpigen_write_name("HCDN");
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acpigen_write_package(HC_POSSIBLE_NUM);
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for(i=0;i<sysconf.hc_possible_num;i++) {
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lenp += acpigen_write_dword(sysconf.hcdn[i]);
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acpigen_write_dword(sysconf.hcdn[i]);
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}
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for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
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lenp += acpigen_write_dword(0x20202020);
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acpigen_write_dword(0x20202020);
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}
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acpigen_patch_len(lenp - 1);
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len += lenp;
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return len;
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acpigen_pop_len();
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}
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static int k8acpi_write_pci_data(int dlen, const char *name, int offset) {
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static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
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device_t dev;
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uint32_t dword;
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int len, lenp, i;
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int i;
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dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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len = acpigen_write_name(name);
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lenp = acpigen_write_package(dlen);
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acpigen_write_name(name);
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acpigen_write_package(dlen);
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for(i=0; i<dlen; i++) {
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dword = pci_read_config32(dev, offset+i*4);
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lenp += acpigen_write_dword(dword);
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acpigen_write_dword(dword);
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}
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// minus the opcode
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acpigen_patch_len(lenp - 1);
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return len + lenp;
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acpigen_pop_len();
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}
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void k8acpi_write_vars(void)
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{
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int lens;
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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lens = acpigen_write_scope(pscope);
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lens += k8acpi_write_pci_data(4, "BUSN", 0xe0);
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lens += k8acpi_write_pci_data(8, "PCIO", 0xc0);
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lens += k8acpi_write_pci_data(16, "MMIO", 0x80);
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lens += acpigen_write_name_byte("SBLK", sysconf.sblk);
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lens += acpigen_write_name_byte("CBST",
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acpigen_write_scope(pscope);
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k8acpi_write_pci_data(4, "BUSN", 0xe0);
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k8acpi_write_pci_data(8, "PCIO", 0xc0);
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k8acpi_write_pci_data(16, "MMIO", 0x80);
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acpigen_write_name_byte("SBLK", sysconf.sblk);
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acpigen_write_name_byte("CBST",
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((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0);
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lens += acpigen_write_name_dword("SBDN", sysconf.sbdn);
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acpigen_write_name_dword("SBDN", sysconf.sbdn);
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msr = rdmsr(TOP_MEM);
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lens += acpigen_write_name_dword("TOM1", msr.lo);
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acpigen_write_name_dword("TOM1", msr.lo);
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msr = rdmsr(TOP_MEM2);
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/*
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* Since XP only implements parts of ACPI 2.0, we can't use a qword
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@ -278,11 +272,11 @@ void k8acpi_write_vars(void)
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* Shift value right by 20 bit to make it fit into 32bit,
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* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
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*/
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lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
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acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
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lens += k8acpi_write_HT();
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k8acpi_write_HT();
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//minus opcode
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acpigen_patch_len(lens - 1);
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acpigen_pop_len();
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}
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void update_ssdtx(void *ssdtx, int i)
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