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amdk8: Move to implicit length patching 

Change-Id: I8b4c36adaa7ea791ae1a8f7c0d059b9201b08f94
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7332
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-11-04 21:18:25 +01:00
parent a09f4db396
commit f8457985d8
5 changed files with 63 additions and 84 deletions
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4
src/cpu/amd/model_10xxx/powernow_acpi.c
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@ -25,7 +25,7 @@
#include <cpu/amd/powernow.h> #include <cpu/amd/powernow.h>
/* FIXME: this should be implemented but right now all boards hardcode it. */ /* FIXME: this should be implemented but right now all boards hardcode it. */
int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{ {
return 0; return;
} }

56
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@ -30,23 +30,23 @@
#include <cpu/amd/amdk8_sysconf.h> #include <cpu/amd/amdk8_sysconf.h>
#include <arch/cpu.h> #include <arch/cpu.h>
static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid, static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
u8 *pstate_fid, u32 *pstate_power, int coreID, u8 *pstate_fid, u32 *pstate_power, int coreID,
u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control) u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control)
{ {
int lenp, lenpr, i; int i;
if ((onlyBSP) && (coreID != 0)) { if ((onlyBSP) && (coreID != 0)) {
plen = 0; plen = 0;
pcontrol_blk = 0; pcontrol_blk = 0;
} }
lenpr = acpigen_write_processor(coreID, pcontrol_blk, plen); acpigen_write_processor(coreID, pcontrol_blk, plen);
lenpr += acpigen_write_empty_PCT(); acpigen_write_empty_PCT();
lenpr += acpigen_write_name("_PSS"); acpigen_write_name("_PSS");
/* add later to total sum */ /* add later to total sum */
lenp = acpigen_write_package(pstate_num); acpigen_write_package(pstate_num);
for (i = 0;i < pstate_num;i++) { for (i = 0;i < pstate_num;i++) {
u32 status, c2; u32 status, c2;
@ -56,7 +56,7 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
(pstate_vid[i] << 6) | (pstate_vid[i] << 6) |
pstate_fid[i]; pstate_fid[i];
lenp += acpigen_write_PSS_package(pstate_feq[i], acpigen_write_PSS_package(pstate_feq[i],
pstate_power[i], pstate_power[i],
0x64, 0x64,
0x7, 0x7,
@ -64,13 +64,11 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
status); status);
} }
/* update the package size */ /* update the package size */
acpigen_patch_len(lenp - 1); acpigen_pop_len();
lenpr += lenp; acpigen_write_PPC(pstate_num);
lenpr += acpigen_write_PPC(pstate_num);
/* patch the whole Processor token length */ /* patch the whole Processor token length */
acpigen_patch_len(lenpr - 2); acpigen_pop_len();
return lenpr;
} }
#if CONFIG_K8_REV_F_SUPPORT #if CONFIG_K8_REV_F_SUPPORT
@ -79,9 +77,8 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
* Two parts are included, the another is the DSDT reconstruction process * Two parts are included, the another is the DSDT reconstruction process
*/ */
static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{ {
int len;
u8 processor_brand[49]; u8 processor_brand[49];
u32 *v, control; u32 *v, control;
struct cpuid_result cpuid1; struct cpuid_result cpuid1;
@ -358,8 +355,6 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
write_pstates: write_pstates:
len = 0;
control = (0x3 << 30) | /* IRT */ control = (0x3 << 30) | /* IRT */
(0x2 << 28) | /* RVO */ (0x2 << 28) | /* RVO */
(0x1 << 27) | /* ExtType */ (0x1 << 27) | /* ExtType */
@ -368,12 +363,10 @@ write_pstates:
(0x5 << 11); /* VST */ (0x5 << 11); /* VST */
for (index = 0; index < (cmp_cap + 1); index++) { for (index = 0; index < (cmp_cap + 1); index++) {
len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
Pstate_fid, Pstate_power, index, Pstate_fid, Pstate_power, index,
pcontrol_blk, plen, onlyBSP, control); pcontrol_blk, plen, onlyBSP, control);
} }
return len;
} }
#else #else
@ -754,13 +747,13 @@ struct cpuentry entr[] = {
{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
}; };
static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{ {
u8 cmp_cap; u8 cmp_cap;
struct cpuentry *data = NULL; struct cpuentry *data = NULL;
uint32_t control; uint32_t control;
int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0; int i = 0, index = 0, Pstate_num = 0, dev = 0;
msr_t msr; msr_t msr;
u8 Pstate_fid[MAXP+1]; u8 Pstate_fid[MAXP+1];
u16 Pstate_feq[MAXP+1]; u16 Pstate_feq[MAXP+1];
@ -773,7 +766,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if((cpuid1.edx & 0x6)!=0x6) { if((cpuid1.edx & 0x6)!=0x6) {
printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n"); printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
return 0; return;
} }
cpuid1 = cpuid(0x80000001); cpuid1 = cpuid(0x80000001);
@ -803,7 +796,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
if (data == NULL) { if (data == NULL) {
printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n"); printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
return 0; return;
} }
#if CONFIG_MAX_PHYSICAL_CPUS #if CONFIG_MAX_PHYSICAL_CPUS
@ -836,8 +829,6 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
* time = value*1uS (often seen value: 2uS) * time = value*1uS (often seen value: 2uS)
*/ */
len = 0;
Pstate_fid[0] = Max_fid; Pstate_fid[0] = Max_fid;
Pstate_feq[0] = fid_to_freq(Max_fid); Pstate_feq[0] = fid_to_freq(Max_fid);
Pstate_vid[0] = Max_vid; Pstate_vid[0] = Max_vid;
@ -864,28 +855,23 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
continue; continue;
for (i = 0; i < (cmp_cap + 1); i++) { for (i = 0; i < (cmp_cap + 1); i++) {
len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
Pstate_fid, Pstate_power, index+i, Pstate_fid, Pstate_power, index+i,
pcontrol_blk, plen, onlyBSP, control); pcontrol_blk, plen, onlyBSP, control);
} }
index += i; index += i;
} }
printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index); printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
return len;
} }
#endif #endif
int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{ {
int lens;
char pscope[] = "\\_PR"; char pscope[] = "\\_PR";
lens = acpigen_write_scope(pscope); acpigen_write_scope(pscope);
lens += pstates_algorithm(pcontrol_blk, plen, onlyBSP); pstates_algorithm(pcontrol_blk, plen, onlyBSP);
//minus opcode acpigen_pop_len();
acpigen_patch_len(lens - 1);
return lens;
} }

2
src/include/cpu/amd/powernow.h
View File

@ -20,6 +20,6 @@
#ifndef POWERNOW_H #ifndef POWERNOW_H
#define POWERNOW_H #define POWERNOW_H
int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP); void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP);
#endif #endif

7
src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
View File

@ -96,14 +96,13 @@ void mainboard_inject_dsdt(void)
global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE); global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE);
if (gnvs) { if (gnvs) {
int scopelen;
memset(gnvs, 0, sizeof(*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_write_gvars(gnvs); acpi_write_gvars(gnvs);
/* Add it to SSDT. */ /* Add it to SSDT. */
scopelen = acpigen_write_scope("\\"); acpigen_write_scope("\\");
scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_write_name_dword("NVSA", (u32) gnvs);
acpigen_patch_len(scopelen - 1); acpigen_pop_len();
} }
} }

64
src/northbridge/amd/amdk8/acpi.c
View File

@ -204,71 +204,65 @@ unsigned long acpi_fill_slit(unsigned long current)
return current; return current;
} }
static int k8acpi_write_HT(void) { static void k8acpi_write_HT(void) {
int len, lenp, i; int i;
len = acpigen_write_name("HCLK"); acpigen_write_name("HCLK");
lenp = acpigen_write_package(HC_POSSIBLE_NUM); acpigen_write_package(HC_POSSIBLE_NUM);
for(i=0;i<sysconf.hc_possible_num;i++) { for(i=0;i<sysconf.hc_possible_num;i++) {
lenp += acpigen_write_dword(sysconf.pci1234[i]); acpigen_write_dword(sysconf.pci1234[i]);
} }
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
lenp += acpigen_write_dword(0x0); acpigen_write_dword(0x0);
} }
acpigen_patch_len(lenp - 1); acpigen_pop_len();
len += lenp;
len += acpigen_write_name("HCDN"); acpigen_write_name("HCDN");
lenp = acpigen_write_package(HC_POSSIBLE_NUM); acpigen_write_package(HC_POSSIBLE_NUM);
for(i=0;i<sysconf.hc_possible_num;i++) { for(i=0;i<sysconf.hc_possible_num;i++) {
lenp += acpigen_write_dword(sysconf.hcdn[i]); acpigen_write_dword(sysconf.hcdn[i]);
} }
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
lenp += acpigen_write_dword(0x20202020); acpigen_write_dword(0x20202020);
} }
acpigen_patch_len(lenp - 1); acpigen_pop_len();
len += lenp;
return len;
} }
static int k8acpi_write_pci_data(int dlen, const char *name, int offset) { static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
device_t dev; device_t dev;
uint32_t dword; uint32_t dword;
int len, lenp, i; int i;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
len = acpigen_write_name(name); acpigen_write_name(name);
lenp = acpigen_write_package(dlen); acpigen_write_package(dlen);
for(i=0; i<dlen; i++) { for(i=0; i<dlen; i++) {
dword = pci_read_config32(dev, offset+i*4); dword = pci_read_config32(dev, offset+i*4);
lenp += acpigen_write_dword(dword); acpigen_write_dword(dword);
} }
// minus the opcode // minus the opcode
acpigen_patch_len(lenp - 1); acpigen_pop_len();
return len + lenp;
} }
void k8acpi_write_vars(void) void k8acpi_write_vars(void)
{ {
int lens;
msr_t msr; msr_t msr;
char pscope[] = "\\_SB.PCI0"; char pscope[] = "\\_SB.PCI0";
lens = acpigen_write_scope(pscope); acpigen_write_scope(pscope);
lens += k8acpi_write_pci_data(4, "BUSN", 0xe0); k8acpi_write_pci_data(4, "BUSN", 0xe0);
lens += k8acpi_write_pci_data(8, "PCIO", 0xc0); k8acpi_write_pci_data(8, "PCIO", 0xc0);
lens += k8acpi_write_pci_data(16, "MMIO", 0x80); k8acpi_write_pci_data(16, "MMIO", 0x80);
lens += acpigen_write_name_byte("SBLK", sysconf.sblk); acpigen_write_name_byte("SBLK", sysconf.sblk);
lens += acpigen_write_name_byte("CBST", acpigen_write_name_byte("CBST",
((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0); ((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0);
lens += acpigen_write_name_dword("SBDN", sysconf.sbdn); acpigen_write_name_dword("SBDN", sysconf.sbdn);
msr = rdmsr(TOP_MEM); msr = rdmsr(TOP_MEM);
lens += acpigen_write_name_dword("TOM1", msr.lo); acpigen_write_name_dword("TOM1", msr.lo);
msr = rdmsr(TOP_MEM2); msr = rdmsr(TOP_MEM2);
/* /*
* Since XP only implements parts of ACPI 2.0, we can't use a qword * Since XP only implements parts of ACPI 2.0, we can't use a qword
@ -278,11 +272,11 @@ void k8acpi_write_vars(void)
* Shift value right by 20 bit to make it fit into 32bit, * Shift value right by 20 bit to make it fit into 32bit,
* giving us 1MB granularity and a limit of almost 4Exabyte of memory. * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
*/ */
lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
lens += k8acpi_write_HT(); k8acpi_write_HT();
//minus opcode //minus opcode
acpigen_patch_len(lens - 1); acpigen_pop_len();
} }
void update_ssdtx(void *ssdtx, int i) void update_ssdtx(void *ssdtx, int i)