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As per suggestion from Yinghai Lu <yinghailu@gmail.com> this patch 

fixes the problems with PCI add-on cards not being detected or
initialized on MCP55-based systems (PCI bridge decoding change).

I have tested this on the MSI MS-7260 (K9N Neo) with a PCI VGA card,
which worked fine in any of the three PCI slots.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-09-25 01:31:35 +00:00
parent 48cac24742
commit f845e02edb
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
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@ -271,6 +271,8 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
#if MCP55_USE_AZA == 1
RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
@ -294,8 +296,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
//Master MCP55 ????YHLU
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),