soc/intel/tigerlake: Add CpuReplacementCheck to chip options

Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.

TEST=boot and verified with volteer

Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/chip.h

@@ -365,6 +365,12 @@ struct soc_intel_tigerlake_config {
 		/* External Vnn Voltage in mV */
 		int vnn_sx_voltage_mv;
 	} ext_fivr_settings;
+
+	/*
+	 * Enable(1)/Disable(0) CPU Replacement check.
+	 * Default 0. Setting this to 1 to check CPU replacement.
+	 */
+	uint8_t CpuReplacementCheck;
 };
 
 typedef struct soc_intel_tigerlake_config config_t;

src/soc/intel/tigerlake/romstage/fsp_params.c

@@ -199,6 +199,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	/* Command Pins Mirrored */
 	m_cfg->CmdMirror[0] = config->CmdMirror;
+
+	/* Skip CPU replacement check */
+	m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)