mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
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@ -214,4 +214,5 @@ chip soc/intel/apollolake
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# Disable compliance mode
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register "DisableComplianceMode" = "1"
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register "disable_xhci_lfps_pm" = "0"
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end
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@ -8,6 +8,7 @@
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#include <delay.h>
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#include <gpio.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/intel/apollolake/chip.h>
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enum {
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SKU_37_DROID = 37, /* LTE */
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@ -74,3 +75,24 @@ void variant_smi_sleep(u8 slp_typ)
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return;
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}
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}
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void variant_update_devtree(struct device *dev)
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{
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struct soc_intel_apollolake_config *cfg = NULL;
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cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
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if (cfg != NULL && cfg->disable_xhci_lfps_pm) {
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switch (google_chromeec_get_board_sku()) {
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case 37:
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case 38:
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case 39:
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case 40:
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cfg->disable_xhci_lfps_pm = 1;
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return;
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default:
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return;
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}
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}
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}
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