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soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabled 

When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM
is enabled.

BUG=b:72728953

Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2018-04-18 16:32:30 -06:00
parent 0f35af8f42
commit f874442553
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/common/block/cpu/car/exit_car.S
View File

@ -22,6 +22,21 @@
.global chipset_teardown_car
chipset_teardown_car:
#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
/*
* Since Page table is located in CAR, disable paging before CAR
* teardown. Also clear CR3 and CR4.PAE.
*/
mov %cr0, %eax
and $(~(CR0_PG)), %eax
mov %eax, %cr0
xor %eax, %eax
mov %eax, %cr3
mov %cr4, %eax
and $(~(CR4_PAE)), %eax
mov %eax, %cr4
#endif
/*
* Retrieve return address from stack as it will get trashed below if
* execution is utilizing the cache-as-ram stack.