mb/ocp/sonorapass: Add Sonora Pass
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
This commit is contained in:
Ryback Hung
Andrey Petrov
parent
d2bbc68fa3
commit
f87ad9225c
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# SPDX-License-Identifier: GPL-2.0-only
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# This file is part of the coreboot project.
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if BOARD_OCP_SONORAPASS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select MAINBOARD_USES_FSP2_0
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select IPMI_KCS
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select SOC_INTEL_COOPERLAKE_SP
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select SUPERIO_ASPEED_AST2400
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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default "ocp/sonorapass"
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config MAINBOARD_PART_NUMBER
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string
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default "SonoraPass"
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config MAINBOARD_FAMILY
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string
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default "SonoraPass"
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
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endif
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config BOARD_OCP_SONORAPASS
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bool "SonoraPass"
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bootblock-y += bootblock.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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Name(\APC1, Zero) // IIO IOAPIC
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Name(\PICM, Zero) // IOAPIC/8259
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Method(_PIC, 1)
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{
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Store(Arg0, PICM)
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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@ -0,0 +1,10 @@
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FLASH@0xfc000000 64M {
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SI_ALL@0x0 0x2fd8000 {
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SI_DESC@0x0 0x1000
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SI_GBE@0x1000 0x2000
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SI_ME@0x3000 0x2fc5000
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}
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FMAP@0x03000000 0x800
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RW_MRC_CACHE@0x3000800 0x10000
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COREBOOT(CBFS)@0x3010800
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}
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Board name: SonoraPass
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Category: server
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#define ASPEED_CONFIG_INDEX 0x2E
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#define ASPEED_CONFIG_DATA 0x2F
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static void enable_espi_lpc_io_windows(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For that end it is wired into BMC virtual port.
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*/
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/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4));
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/* LPC I/O enable: com1 and com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
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/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
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pci_mmio_write_config32(PCH_DEV_LPC, 0x80,
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(1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4));
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}
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static uint8_t com_to_ast_sio(uint8_t com)
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{
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switch (com) {
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case 0:
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return AST2400_SUART1;
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case 1:
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return AST2400_SUART2;
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case 2:
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return AST2400_SUART3;
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case 4:
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return AST2400_SUART4;
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default:
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return AST2400_SUART1;
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}
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}
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void bootblock_mainboard_early_init(void)
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{
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/* Open IO windows */
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enable_espi_lpc_io_windows();
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/* Configure appropriate physical port of SuperIO chip off BMC */
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const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX,
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com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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/* Port 80h direct to GPIO for LED display */
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const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO);
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aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH);
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/* Enable UART function pin*/
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aspeed_enable_uart_pin(serial_dev);
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}
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@ -0,0 +1,39 @@
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chip soc/intel/xeon_sp/cpx
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 04.0 on end
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device pci 04.1 on end
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device pci 04.2 on end
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device pci 04.3 on end
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device pci 04.4 on end
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device pci 04.5 on end
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device pci 04.6 on end
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device pci 04.7 on end
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device pci 05.0 on end
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device pci 05.2 on end
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device pci 05.4 on end
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device pci 08.0 on end
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device pci 08.1 on end
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device pci 08.2 on end
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device pci 11.0 on end
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device pci 11.1 on end
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device pci 11.5 on end
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device pci 14.0 on end
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device pci 16.0 on end
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device pci 16.1 on end
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device pci 16.4 on end
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device pci 17.0 on end
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device pci 1c.0 on end
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device pci 1c.4 on end
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device pci 1f.2 on end
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device pci 1f.4 on end
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device pci 1f.5 on end
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device pci 1f.0 on # LPC/eSPI Interface
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end
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end
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end
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@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <arch/acpi.h>
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#include <soc/iomap.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include "acpi/platform.asl"
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Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
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Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
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Scope (\_SB)
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{
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Device (PCI0)
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{
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#include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl>
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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}
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Device (UNC0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_UID, 0x3F)
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Method (_BBN, 0, NotSerialized)
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{
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Return (0xff)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0xf)
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}
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Name (_CRS, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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0x00FF, // Range Minimum
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0x00FF, // Range Maximum
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0x0000, // Translation Offset
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0x0001, // Length
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,, )
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})
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}
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}
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}
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