soc/intel/quark: Add EHCI errata
Move the EHCI errata from QuarkFSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14940 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
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@ -24,12 +24,25 @@
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#define USB2_PLL2 0x7F03
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#define USB2_COMPBG 0x7F04
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/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
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#define EHCI_OUT_THRESHOLD_VALUE 0x7f
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#define EHCI_IN_THRESHOLD_VALUE 0x7f
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/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
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* reference clock and Port2 as a USB device port, the following sequence must
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* be followed
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*/
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static const struct reg_script init_script[] = {
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/* Set packet buffer OUT/IN thresholds */
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REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
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~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
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| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
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(EHCI_OUT_THRESHOLD_VALUE
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<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
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| (EHCI_IN_THRESHOLD_VALUE
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<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
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/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
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* For port 0 & 1 as host and port 2 as device.
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*/
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