From f888c682f80e950ef981251f3234569f3c367fc1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 5 Oct 2021 21:37:33 -0700 Subject: [PATCH] soc/intel/alderlake: Enable support for CSE stitching This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions. BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC. BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP. BUG=b:189177580,b:189177538 Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Kconfig | 7 +++++++ src/soc/intel/alderlake/Makefile.inc | 23 +++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a57d05e660..530e76859b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -321,4 +321,11 @@ config SOC_INTEL_CRASHLOG help Enables CrashLog. +if STITCH_ME_BIN + +config CSE_BPDT_VERSION + default "1.7" + +endif + endif diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index c7e0abc492..728c58c967 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -56,4 +56,27 @@ smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include + +ifeq ($(CONFIG_STITCH_ME_BIN),y) + +$(call cse_add_dummy_to_bp1_bp2,DLMP) +$(call cse_add_dummy_to_bp1_bp2,IFPP) +$(call cse_add_dummy_to_bp1_bp2,SBDT) +$(call cse_add_decomp_to_bp1_bp2,RBEP) +$(call cse_add_dummy_to_bp1_bp2,UFSP) +$(call cse_add_dummy_to_bp1_bp2,UFSG) +$(call cse_add_dummy_to_bp1_bp2,OEMP) +$(call cse_add_input_to_bp1_bp2,PMCP) +$(call cse_add_decomp,bp1,MFTP) +$(call cse_add_decomp,bp2,FTPR) +$(call cse_add_input_to_bp1_bp2,IOMP) +$(call cse_add_input_to_bp1_bp2,NPHY) +$(call cse_add_input_to_bp1_bp2,TBTP) +$(call cse_add_input_to_bp1_bp2,PCHC) +$(call cse_add_decomp,bp2,NFTP) +$(call cse_add_dummy,bp2,ISHP) +$(call cse_add_input,bp2,IUNP) + +endif + endif