google/kukui: Notify EC that AP is in S0
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side, pad R23) that is supposed to be high in S0, and low in S3 (and X/don't care in S5). This should be set as early as possible in bootblock. BUG=b:113367227 TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high. BRANCH=None Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
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@ -21,6 +21,7 @@
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#include "gpio.h"
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#include "gpio.h"
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#define BOOTBLOCK_EN_L (GPIO(KPROW0))
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#define BOOTBLOCK_EN_L (GPIO(KPROW0))
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#define AP_IN_SLEEP_L (GPIO(SRCLKENA0))
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void bootblock_mainboard_init(void)
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void bootblock_mainboard_init(void)
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{
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{
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@ -29,6 +30,9 @@ void bootblock_mainboard_init(void)
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/* Turn on real eMMC. */
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/* Turn on real eMMC. */
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gpio_output(BOOTBLOCK_EN_L, 1);
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gpio_output(BOOTBLOCK_EN_L, 1);
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/* Declare we are in S0 */
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gpio_output(AP_IN_SLEEP_L, 1);
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
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mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
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mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
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}
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}
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