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mainboard/google/snappy: Update WDT touchscreen device 

Export PowerResource for WDT touchscreen device.

BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Compiles successfully.

Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18240
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-01-25 19:29:06 -08:00 committed by Aaron Durbin
parent a7a517ddc5
commit f8ab456a63
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/reef/variants/snappy/devicetree.cb
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@ -188,6 +188,11 @@ chip soc/intel/apollolake
register "generic.irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "generic.irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
register "generic.probed" = "1" register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "20"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x20" register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end device i2c 2c on end
end end