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- unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY 

- cleanup reset
- some minor warning fixes.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-07 00:38:09 +00:00 committed by Stefan Reinauer
parent 0ff769baa5
commit f8b1923848
23 changed files with 32 additions and 138 deletions
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5
src/mainboard/asus/a8n_e/Kconfig
View File

@ -44,11 +44,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_ASUS_A8N_E
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_ASUS_A8N_E
config MAINBOARD_PART_NUMBER
string
default "A8N-E"

5
src/mainboard/asus/a8v-e_se/Kconfig
View File

@ -44,11 +44,6 @@ config SB_HT_CHAIN_ON_BUS0
default 1
depends on BOARD_ASUS_A8V_E_SE
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_ASUS_A8V_E_SE
config MAINBOARD_PART_NUMBER
string
default "A8V-E SE"

5
src/mainboard/asus/m2v-mx_se/Kconfig
View File

@ -86,11 +86,6 @@ config HT_CHAIN_UNITID_BASE
default 0x0
depends on BOARD_ASUS_M2V_MX_SE
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_ASUS_M2V_MX_SE
config SB_HT_CHAIN_ON_BUS0
int
default 1

5
src/mainboard/hp/dl145_g3/Kconfig
View File

@ -47,11 +47,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_HP_DL145_G3
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_HP_DL145_G3
config MAINBOARD_PART_NUMBER
string
default "ProLiant DL145 G3"

5
src/mainboard/msi/ms7135/Kconfig
View File

@ -79,11 +79,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_MSI_MS7135
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_MSI_MS7135
config IRQ_SLOT_COUNT
int
default 13

25
src/mainboard/msi/ms9282/get_bus_conf.c
View File

@ -68,31 +68,6 @@ extern void get_sblk_pci1234(void);
static unsigned get_bus_conf_done = 0;
static unsigned get_hcid(unsigned i)
{
unsigned id = 0;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff;
device_t dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
switch (dev->device) {
case 0x0369: //IO55
id = 4;
break;
}
// we may need more way to find out hcid: subsystem id? GPIO read ?
// we need use id for 1. bus num, 2. mptable, 3. acpi table
return id;
}
void get_bus_conf(void)
{

8
src/mainboard/msi/ms9282/mptable.c
View File

@ -38,12 +38,12 @@ static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "MSI ";
static const char productid[12] = "MS9282 ";
static const char productid[12] = "MS9282 ";
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
struct mb_sysconf_t *m;
unsigned sbdn;
int i,j;
int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));

6
src/mainboard/msi/ms9652_fam10/Kconfig
View File

@ -16,6 +16,7 @@ config BOARD_MSI_MS9652_FAM10
select ENABLE_APIC_EXT_ID
select AMDMCT
select TINY_BOOTBLOCK
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
config MAINBOARD_DIR
string
@ -189,11 +190,6 @@ config SB_HT_CHAIN_ON_BUS0
default 1
depends on BOARD_MSI_MS9652_FAM10
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default y
depends on BOARD_MSI_MS9652_FAM10
config VAR_MTRR_HOLE
bool
default n

5
src/mainboard/sunw/ultra40/Kconfig
View File

@ -44,11 +44,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_SUNW_ULTRA40
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUNW_ULTRA40
config MAINBOARD_PART_NUMBER
string
default "Ultra 40"

5
src/mainboard/supermicro/h8dme/Kconfig
View File

@ -51,11 +51,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_SUPERMICRO_H8DME
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUPERMICRO_H8DME
config MAINBOARD_PART_NUMBER
string
default "H8DME-2"

5
src/mainboard/supermicro/h8dmr/Kconfig
View File

@ -50,11 +50,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_SUPERMICRO_H8DMR
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUPERMICRO_H8DMR
config MAINBOARD_PART_NUMBER
string
default "H8DMR-i2"

5
src/mainboard/supermicro/h8dmr_fam10/Kconfig
View File

@ -68,11 +68,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config MAINBOARD_PART_NUMBER
string
default "H8DMR-i2 (Fam10)"

5
src/mainboard/supermicro/h8qme_fam10/Kconfig
View File

@ -69,11 +69,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_SUPERMICRO_H8QME_FAM10
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUPERMICRO_H8QME_FAM10
config MAINBOARD_PART_NUMBER
string
default "H8QME-2+ (Fam10)"

6
src/mainboard/tyan/s2850/Kconfig
View File

@ -10,6 +10,7 @@ config BOARD_TYAN_S2850
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
config MAINBOARD_DIR
string
@ -56,11 +57,6 @@ config HT_CHAIN_END_UNITID_BASE
default 0x20
depends on BOARD_TYAN_S2850
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default y
depends on BOARD_TYAN_S2850
config SB_HT_CHAIN_ON_BUS0
int
default 0

6
src/mainboard/tyan/s2875/Kconfig
View File

@ -11,6 +11,7 @@ config BOARD_TYAN_S2875
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
config MAINBOARD_DIR
string
@ -62,11 +63,6 @@ config HT_CHAIN_END_UNITID_BASE
default 0x20
depends on BOARD_TYAN_S2875
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default y
depends on BOARD_TYAN_S2875
config SB_HT_CHAIN_ON_BUS0
int
default 0

5
src/mainboard/tyan/s2892/Kconfig
View File

@ -75,11 +75,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_TYAN_S2892
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_TYAN_S2892
config IRQ_SLOT_COUNT
int
default 11

5
src/mainboard/tyan/s2895/Kconfig
View File

@ -75,11 +75,6 @@ config SB_HT_CHAIN_ON_BUS0
default 2
depends on BOARD_TYAN_S2895
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_TYAN_S2895
config IRQ_SLOT_COUNT
int
default 11

5
src/northbridge/amd/amdfam10/Kconfig
View File

@ -57,4 +57,9 @@ config BOOTBLOCK_NORTHBRIDGE_INIT
default "northbridge/amd/amdfam10/bootblock.c"
depends on NORTHBRIDGE_AMD_AMDFAM10
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on NORTHBRIDGE_AMD_AMDFAM10
source src/northbridge/amd/amdfam10/root_complex/Kconfig

5
src/northbridge/amd/amdk8/Kconfig
View File

@ -47,4 +47,9 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
default n
depends on NORTHBRIDGE_AMD_AMDK8
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on NORTHBRIDGE_AMD_AMDK8
source src/northbridge/amd/amdk8/root_complex/Kconfig

29
src/northbridge/amd/amdk8/reset_test.c
View File

@ -7,9 +7,9 @@
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
static int cpu_init_detected(unsigned nodeid)
static inline int cpu_init_detected(unsigned nodeid)
{
unsigned long htic;
u32 htic;
device_t dev;
dev = PCI_DEV(0, 0x18 + nodeid, 0);
@ -18,25 +18,25 @@ static int cpu_init_detected(unsigned nodeid)
return !!(htic & HTIC_INIT_Detect);
}
static int bios_reset_detected(void)
static inline int bios_reset_detected(void)
{
unsigned long htic;
u32 htic;
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
}
static int cold_reset_detected(void)
static inline int cold_reset_detected(void)
{
unsigned long htic;
u32 htic;
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
return !(htic & HTIC_ColdR_Detect);
}
static void distinguish_cpu_resets(unsigned nodeid)
static inline void distinguish_cpu_resets(unsigned nodeid)
{
uint32_t htic;
u32 htic;
device_t device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
htic = pci_read_config32(device, HT_INIT_CONTROL);
@ -46,7 +46,7 @@ static void distinguish_cpu_resets(unsigned nodeid)
static void set_bios_reset(void)
{
unsigned long htic;
u32 htic;
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
@ -54,10 +54,10 @@ static void set_bios_reset(void)
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
unsigned reg;
u8 reg;
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
unsigned config_map;
u32 config_map;
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
@ -71,17 +71,16 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
return 0;
}
static unsigned get_sblk(void)
static inline unsigned get_sblk(void)
{
uint32_t reg;
u32 reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3) ;
}
static unsigned get_sbbusn(unsigned sblk)
static inline unsigned get_sbbusn(unsigned sblk)
{
return node_link_to_bus(0, sblk);
}

1
src/southbridge/nvidia/mcp55/mcp55_reset.c
View File

@ -22,6 +22,7 @@
*/
#include <arch/io.h>
#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
(((BUS) & 0xFFF) << 20) | \

2
src/southbridge/nvidia/mcp55/mcp55_smbus.c
View File

@ -100,7 +100,6 @@ unsigned pm_base;
static void mcp55_sm_read_resources(device_t dev)
{
struct resource *res;
unsigned long index;
/* Get the normal pci resources of this device */
@ -110,7 +109,6 @@ static void mcp55_sm_read_resources(device_t dev)
pci_get_resource(dev, index);
}
compact_resources(dev);
}
static void mcp55_sm_init(device_t dev)

17
src/southbridge/nvidia/mcp55/mcp55_smbus.h
View File

@ -40,23 +40,6 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(smbus_io_base + SMBHSTSTAT);
val &= 0x1f;
if (val == 0) {
return 0;
}
outb(val,smbus_io_base + SMBHSTSTAT);
} while(--loops);
return -2;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
{
unsigned long loops;