Fix support for RAM-less multi-processor init
Fix regression after commit:
7dfe32c540
Only align 16-bit entry on platforms that really require it,
indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig.
Disable assertion test of AP_SIPI_VECTOR for platforms not
depending on this feature.
Build of romstage should be fixed to get the vector address from
bootblock build automatically.
Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/875
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
parent
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@ -8,6 +8,13 @@ config AP_IN_SIPI_WAIT
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default n
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depends on ARCH_X86
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# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
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# can boot AP CPUs to enable their shared caches.
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config SIPI_VECTOR_IN_ROM
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bool
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default n
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depends on ARCH_X86
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config RAMBASE
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hex
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default 0x100000
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@ -30,10 +30,11 @@ TARGET(binary)
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SECTIONS
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{
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/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
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* with Startup IPI message without RAM.
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* with Startup IPI message without RAM. Align .rom to next 4 byte
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* boundary anyway, so no pad byte appears between _rom and _start.
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*/
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.bogus ROMLOC_MIN : {
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. = ALIGN(4096);
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. = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
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ROMLOC = .;
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} >rom = 0xff
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@ -52,11 +53,14 @@ SECTIONS
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* may cause the total size of a section to change when the start
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* address gets applied.
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*/
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ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
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ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
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(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
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/* Post-check proper SIPI vector. */
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_bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment");
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_bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR");
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_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),
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"Bad SIPI vector alignment");
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_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR),
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"Address mismatch on AP_SIPI_VECTOR");
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/DISCARD/ : {
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*(.comment)
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@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
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select MMX
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select SSE
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select UDELAY_TSC
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select SIPI_VECTOR_IN_ROM
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# mPGA604 are usually Intel Netburst CPUs which should have SSE2
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# but the ramtest.c code on the Dell S1850 seems to choke on
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