GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/broadwell: Drop `gpu_panel_port_select` 

The corresponding bits in PP_ON_DELAYS are reserved MBZ.

Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-09-02 18:54:03 +02:00 committed by Patrick Georgi
parent 657edbeea4
commit f8d47455f7
9 changed files with 7 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/auron/variants/auron_paine/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/broadwell
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/broadwell
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/auron/variants/buddy/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/broadwell
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/auron/variants/gandof/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/broadwell
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/auron/variants/lulu/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/broadwell
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/auron/variants/samus/overridetree.cb
View File

@ -3,8 +3,7 @@ chip soc/intel/broadwell
# Enable DDI2 Hotplug with 6ms pulse
register "gpu_dp_c_hotplug" = "0x06"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms

3
src/mainboard/purism/librem_bdw/devicetree.cb
View File

@ -9,8 +9,7 @@ chip soc/intel/broadwell
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
# Set panel power delays
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms

1
src/soc/intel/broadwell/chip.h
View File

@ -84,7 +84,6 @@ struct soc_intel_broadwell_config {
u8 gpu_dp_d_hotplug;
/* Panel power sequence timings */
u8 gpu_panel_port_select;
u8 gpu_panel_power_cycle_delay;
u16 gpu_panel_power_up_delay;
u16 gpu_panel_power_down_delay;

1
src/soc/intel/broadwell/igd.c
View File

@ -298,7 +298,6 @@ static void igd_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
gtt_write(PCH_PP_ON_DELAYS, reg32);