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soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macro 

This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.

BUG=none
TEST=Able to build and boot taeko, google board.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-05-23 11:53:17 +05:30
parent b60e69bde8
commit f8d4b50a67
1 changed files with 0 additions and 1 deletions
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1
src/soc/intel/alderlake/include/soc/pci_devs.h
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@ -211,7 +211,6 @@
#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) #define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3)
#define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_ESPI 0x1f
#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI
#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) #define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0)
#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) #define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1)
#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) #define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2)