mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boards

When GPIO_2 was configured as PAD_NF with the WAKE_L function selected
the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the
corresponding SCI mapping register, but didn't set up the SCI level and
trigger type, so that couldn't have worked on most of the boards. The
only boards where I think this was actually tested are the google/zork
ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is
GPIO mode instead of the WAKE_L mode, but at least the SCI was
configured correctly. The new PAD_NF_SCI macro can configure both the
right GPIO mux setting and set up the SCI configuration correctly, so
use this new macro for the GPIO_2 pin. For test purposes I also added
the corresponding GPIO_2 configuration to amd/mandolin to see if the
affected registers end up having the expected value using the HDT
debugger to look at the registers, but didn't test the wake-up
functionality, since S3 resume isn't working on amd/mandolin yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/amd/mandolin/variants/mandolin/gpio.c

@@ -9,6 +9,8 @@
  * ramstage.
  */
 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+	/* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL, SCI */
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW),
 	/* SSD DEVSLP */
 	PAD_NF(GPIO_5, DEVSLP0, PULL_NONE),
 	/* Defeature SATA Express DEVSLP, as some boards are reworked

src/mainboard/amd/padmelon/gpio.c

@@ -28,8 +28,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* WLAND */
 	PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3),
 #else
-	/* PCIE_WAKE */
+	/* PCIE_WAKE, SCI */
-	PAD_GPI(GPIO_2, PULL_DOWN),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW),
 	/* DEVSLP1 - default as GPIO, do not program */
 
 	/* WLAND - default as GPIO, do not program */

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -12,7 +12,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	/* SYS_RESET_L */
 	PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
 	/* WAKE_L */
-	PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
 	/* GSC_SOC_INT_L */
 	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
 	/* SOC_PEN_DETECT_ODL */

src/mainboard/google/kahlee/variants/baseboard/gpio.c

@@ -81,7 +81,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP),
 
 	/* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */
-	PAD_NF(GPIO_2, WAKE_L, PULL_UP),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW),
 
 	/* GPIO_3 - MEM_VOLT_SEL */
 	PAD_GPI(GPIO_3, PULL_UP),

src/mainboard/google/mancomb/variants/baseboard/gpio.c

@@ -12,7 +12,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	/* SYS_RESET_L */
 	PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
 	/* WAKE_L */
-	PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
 	/* GSC_SOC_INT_L */
 	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
 	/* AGPIO4 */

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

@@ -14,7 +14,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* SYS_RESET_L */
 	PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
 	/* WIFI_PCIE_WAKE_ODL */
-	PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
 	/* H1_FCH_INT_ODL */
 	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
 	/* PEN_DETECT_ODL */

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c

@@ -16,7 +16,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* SYS_RESET_L */
 	PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
 	/* WIFI_PCIE_WAKE_ODL */
-	PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
+	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
 	/* H1_FCH_INT_ODL */
 	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
 	/* PEN_DETECT_ODL */