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AGESA: Drop old ACPI S3 resume path 

Fixed ACPI S3 support will use POSTCAR_STAGE and no longer
uses the code removed here.

Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-09-03 13:44:03 +03:00
parent 740afc4dde
commit f8e9449df0
4 changed files with 0 additions and 60 deletions
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1
src/cpu/amd/agesa/Makefile.inc
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@ -18,7 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
ramstage-y += s3_mtrr.c ramstage-y += s3_mtrr.c
ifeq ($(CONFIG_AGESA_LEGACY), y) ifeq ($(CONFIG_AGESA_LEGACY), y)

4
src/cpu/amd/agesa/romstage.c
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@ -17,7 +17,6 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cbmem.h> #include <cbmem.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <console/console.h> #include <console/console.h>
@ -130,8 +129,5 @@ void asmlinkage romstage_after_car(void)
if (HAS_LEGACY_WRAPPER) if (HAS_LEGACY_WRAPPER)
agesa_postcar(cb); agesa_postcar(cb);
if (!IS_ENABLED(CONFIG_CPU_AMD_PI) && cb->s3resume)
set_resume_cache();
run_ramstage(); run_ramstage();
} }

53
src/cpu/amd/agesa/s3_resume.c
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@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
#include <cbmem.h>
#include <program_loading.h>
#include <string.h>
#include <halt.h>
#include "s3_resume.h"
#include <northbridge/amd/agesa/agesa_helper.h>
void set_resume_cache(void)
{
msr_t msr;
/* disable fixed mtrr for now, it will be enabled by mtrr restore */
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default memory type and disable fixed and enable variable MTRRs */
msr.hi = 0;
msr.lo = (1 << 11);
wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache();
}

2
src/cpu/amd/agesa/s3_resume.h
View File

@ -17,8 +17,6 @@
#define S3_RESUME_H #define S3_RESUME_H
void restore_mtrr(void); void restore_mtrr(void);
void prepare_for_resume(void);
void set_resume_cache(void);
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
const void *OemS3Saved_MTRR_Storage(void); const void *OemS3Saved_MTRR_Storage(void);