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Rename almost all occurences of LinuxBIOS to coreboot. 

Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2008-01-18 15:08:58 +00:00 committed by Stefan Reinauer
parent 7e61e45402
commit f8ee1806ac
388 changed files with 1718 additions and 1718 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
NEWS
View File

@ -1,6 +1,6 @@
- 2.0.0
- this NEWS file is neglected in favor of the svn commit logs.
See http://snapshots.linuxbios.org/
See http://tracker.coreboot.org/
- 1.1.8
- Store everything in arch
- 1.1.7

26
README
View File

@ -1,8 +1,8 @@
-------------------------------------------------------------------------------
LinuxBIOS README
Coreboot README
-------------------------------------------------------------------------------
LinuxBIOS is a Free Software project aimed at replacing the proprietary
Coreboot is a Free Software project aimed at replacing the proprietary
BIOS you can find in most of today's computers.
It performs just a little bit of hardware initialization and then executes
@ -13,7 +13,7 @@ Payloads
--------
After the basic initialization of the hardware has been performed, any
desired "payload" can be started by LinuxBIOS. Examples include:
desired "payload" can be started by coreboot. Examples include:
* A Linux kernel
* FILO (a simple bootloader with filesystem support)
@ -31,39 +31,39 @@ desired "payload" can be started by LinuxBIOS. Examples include:
Supported Hardware
------------------
LinuxBIOS supports a wide range of chipsets, devices, and mainboards.
Coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
* http://www.linuxbios.org/Supported_Motherboards
* http://www.linuxbios.org/Supported_Chipsets_and_Devices
* http://www.coreboot.org/Supported_Motherboards
* http://www.coreboot.org/Supported_Chipsets_and_Devices
Website and Mailing List
------------------------
Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the LinuxBIOS website:
guidelines and more can be found on the coreboot website:
http://www.linuxbios.org
http://www.coreboot.org
You can contact us directly on the LinuxBIOS mailing list:
You can contact us directly on the coreboot mailing list:
http://www.linuxbios.org/Mailinglist
http://www.coreboot.org/Mailinglist
Copyright and License
---------------------
The copyright on LinuxBIOS is owned by quite a large number of individual
The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.
LinuxBIOS is licensed under the terms of the GNU General Public License (GPL).
Coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files (mostly those derived from the Linux kernel) are licensed under
the "GPL, version 2". For some parts, which were derived from other projects,
other (GPL-compatible) licenses may apply. Please check the individual
source files for details.
This makes the resulting LinuxBIOS images licensed under the GPL, version 2.
This makes the resulting coreboot images licensed under the GPL, version 2.

4
documentation/LinuxBIOS-AMD64.tex
View File

@ -374,7 +374,7 @@ path to a static elf binary (i.e Linux kernel or etherboot)
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
option COREBOOT_EXTRA_VERSION=".0Normal"
mainboard amd/solo
payload /suse/stepan/tg3ide_
disk.zelf
@ -471,7 +471,7 @@ Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
Default image size. Defaults to \texttt{65535} bytes.
\item \begin{verbatim}LINUXBIOS_EXTRA_VERSION\end{verbatim}
\item \begin{verbatim}COREBOOT_EXTRA_VERSION\end{verbatim}
LinuxBIOS extra version. This option has an empty string as default. Set
to any string to add an extra version string to your LinuxBIOS build.

2
documentation/RFC/config.tex
View File

@ -281,7 +281,7 @@ export CONFIG_MAX_CPUS:=1
export HEAP_SIZE:=8192
export STACK_SIZE:=8192
export MEMORY_HOLE:=0
export LINUXBIOS_VERSION:=1.1.0
export COREBOOT_VERSION:=1.1.0
export CC:=$(CROSS_COMPILE)gcc
\end{verbatim}

24
src/arch/i386/Config.lb
View File

@ -22,12 +22,12 @@ else
end
makerule all
depends "linuxbios.rom"
depends "coreboot.rom"
end
makerule floppy
depends "all"
action "mcopy -o linuxbios.rom a:"
action "mcopy -o coreboot.rom a:"
end
makerule nrv2b
@ -55,7 +55,7 @@ end
# this one example shows the mess that has occurred. People are now mixing
# conditional if in the make style with if in the config language style.
# The -1 is linux standard.
# I don't much like it but it is the mode nowadays. So linuxbios will change
# I don't much like it but it is the mode nowadays. So coreboot will change
# what a mess. -- RGM
# catch the case where there is no compression
makedefine PAYLOAD-1:=payload
@ -70,16 +70,16 @@ if CONFIG_PRECOMPRESSED_PAYLOAD
end
if USE_FAILOVER_IMAGE
makedefine LINUXBIOS_APC:=
makedefine LINUXBIOS_RAM_ROM:=
makedefine COREBOOT_APC:=
makedefine COREBOOT_RAM_ROM:=
makerule linuxbios.rom
depends "linuxbios.strip"
makerule coreboot.rom
depends "coreboot.strip"
action "cp $< $@"
end
else
makerule linuxbios.rom
depends "linuxbios.strip buildrom $(PAYLOAD-1)"
makerule coreboot.rom
depends "coreboot.strip buildrom $(PAYLOAD-1)"
action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
end
end
@ -98,10 +98,10 @@ if CONFIG_USE_INIT
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end
makerule linuxbios
depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
makerule coreboot
depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end
end

2
src/arch/i386/boot/acpi.c
View File

@ -1,5 +1,5 @@
/*
* LinuxBIOS ACPI Table support
* coreboot ACPI Table support
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG
* (C) 2005 Stefan Reinauer

20
src/arch/i386/boot/boot.c
View File

@ -113,8 +113,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" addl 12(%%esp), %%eax\n\t"
" addl 8(%%esp), %%eax\n\t"
" movl %%eax, 20(%%esp)\n\t"
/* Place a copy of linuxBIOS in it's new location */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Place a copy of coreboot in it's new location */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 12(%%esp), %%edi\n\t"
" addl 8(%%esp), %%edi\n\t"
" movl 16(%%esp), %%esi\n\t"
@ -122,16 +122,16 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
/* Adjust the stack pointer to point into the new linuxBIOS image */
/* Adjust the stack pointer to point into the new coreboot image */
" addl 20(%%esp), %%esp\n\t"
/* Adjust the instruction pointer to point into the new linuxBIOS image */
/* Adjust the instruction pointer to point into the new coreboot image */
" movl $1f, %%eax\n\t"
" addl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
"1: \n\t"
/* Copy the linuxBIOS bounce buffer over linuxBIOS */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Copy the coreboot bounce buffer over coreboot */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" movl 8(%%esp), %%ecx\n\t"
@ -147,8 +147,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" cli \n\t"
" cld \n\t"
/* Copy the saved copy of linuxBIOS where linuxBIOS runs */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Copy the saved copy of coreboot where coreboot runs */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" addl 8(%%esp), %%esi\n\t"
@ -156,10 +156,10 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
/* Adjust the stack pointer to point into the old linuxBIOS image */
/* Adjust the stack pointer to point into the old coreboot image */
" subl 20(%%esp), %%esp\n\t"
/* Adjust the instruction pointer to point into the old linuxBIOS image */
/* Adjust the instruction pointer to point into the old coreboot image */
" movl $1f, %%eax\n\t"
" subl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"

34
src/arch/i386/boot/linuxbios_table.c
View File

@ -122,16 +122,16 @@ void lb_strings(struct lb_header *header)
uint32_t tag;
const char *string;
} strings[] = {
{ LB_TAG_VERSION, linuxbios_version, },
{ LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
{ LB_TAG_BUILD, linuxbios_build, },
{ LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
{ LB_TAG_COMPILE_BY, linuxbios_compile_by, },
{ LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
{ LB_TAG_COMPILER, linuxbios_compiler, },
{ LB_TAG_LINKER, linuxbios_linker, },
{ LB_TAG_ASSEMBLER, linuxbios_assembler, },
{ LB_TAG_VERSION, coreboot_version, },
{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
{ LB_TAG_BUILD, coreboot_build, },
{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
{ LB_TAG_COMPILER, coreboot_compiler, },
{ LB_TAG_LINKER, coreboot_linker, },
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@ -201,7 +201,7 @@ unsigned long lb_table_fini(struct lb_header *head)
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
@ -315,8 +315,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
lb_cleanup_memory_ranges(mem);
}
/* Routines to extract part so the linuxBIOS table or
* information from the linuxBIOS table after we have written it.
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
@ -348,7 +348,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
return mem;
}
unsigned long write_linuxbios_table(
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
@ -383,7 +383,7 @@ unsigned long write_linuxbios_table(
rec_dest = lb_new_record(head);
rec_src = (struct lb_record *)(void *)&option_table;
memcpy(rec_dest, rec_src, rec_src->size);
/* Create cmos checksum entry in linuxbios table */
/* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
}
#endif
@ -401,9 +401,9 @@ unsigned long write_linuxbios_table(
/* Note:
* I assume that there is always memory at immediately after
* the low_table_end. This means that after I setup the linuxbios table.
* the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
* size of the linuxbios table.
* size of the coreboot table.
*/
/* Record our motheboard */

14
src/arch/i386/boot/linuxbios_table.h
View File

@ -1,10 +1,10 @@
#ifndef LINUXBIOS_TABLE_H
#define LINUXBIOS_TABLE_H
#ifndef COREBOOT_TABLE_H
#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
/* This file holds function prototypes for building the linuxbios table. */
unsigned long write_linuxbios_table(
/* This file holds function prototypes for building the coreboot table. */
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@ -19,11 +19,11 @@ void lb_memory_range(struct lb_memory *mem,
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
/* Routines to extract part so the linuxBIOS table or information
* from the linuxBIOS table.
/* Routines to extract part so the coreboot table or information
* from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
#endif /* LINUXBIOS_TABLE_H */
#endif /* COREBOOT_TABLE_H */

8
src/arch/i386/boot/tables.c
View File

@ -23,7 +23,7 @@ struct gdtarg {
// Copy GDT to new location and reload it
// 2003-07 by SONE Takeshi
// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
void move_gdt(unsigned long newgdt)
{
uint16_t num_gdt_bytes = &gdt_end - &gdt;
@ -58,7 +58,7 @@ struct lb_memory *write_tables(void)
/* Write ACPI tables */
/* write them in the rom area because DSDT can be large (8K on epia-m) which
* pushes linuxbios table out of first 4K if set up in low table area
* pushes coreboot table out of first 4K if set up in low table area
*/
rom_table_end = write_acpi_tables(rom_table_end);
rom_table_end = (rom_table_end+1023) & ~1023;
@ -105,8 +105,8 @@ struct lb_memory *write_tables(void)
move_gdt(low_table_end);
low_table_end += &gdt_end - &gdt;
/* The linuxbios table must be in 0-4K or 960K-1M */
write_linuxbios_table(low_table_start, low_table_end,
/* The coreboot table must be in 0-4K or 960K-1M */
write_coreboot_table(low_table_start, low_table_end,
rom_table_start, rom_table_end);
return get_lb_mem();

2
src/arch/i386/include/arch/acpi.h
View File

@ -1,5 +1,5 @@
/*
* Initial LinuxBIOS ACPI Support - headers and defines.
* coreboot ACPI Support - headers and defines.
*
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG

2
src/arch/i386/include/arch/romcc_io.h
View File

@ -84,7 +84,7 @@ static inline int log2f(int value)
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G,
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/

8
src/arch/i386/init/crt0.S.lb
View File

@ -16,7 +16,7 @@
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
* - Merged the nrv2b decompressor into crt0.base of LinuxBIOS
* - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
@ -65,7 +65,7 @@ __main:
cld /* clear direction flag */
/* copy linuxBIOS from it's initial load location to
/* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
@ -215,8 +215,8 @@ crt_console_tx_string:
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
str_copying_to_ram: .string "Copying LinuxBIOS to RAM.\r\n"
str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */

6
src/arch/i386/init/ldscript.lb
View File

@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*
@ -32,14 +32,14 @@ ENTRY(_start)
*/
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}

4
src/arch/i386/init/ldscript_apc.lb
View File

@ -1,9 +1,9 @@
INPUT(linuxbios_apc.rom)
INPUT(coreboot_apc.rom)
SECTIONS
{
.apcrom . : {
_apcrom = .;
linuxbios_apc.rom(*)
coreboot_apc.rom(*)
_eapcrom = .;
}
_iseg_apc = DCACHE_RAM_BASE;

2
src/arch/i386/init/ldscript_failover.lb
View File

@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*

6
src/arch/i386/init/ldscript_fallback.lb
View File

@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*
@ -32,14 +32,14 @@ ENTRY(_start)
*/
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}

4
src/arch/i386/lib/c_start.S
View File

@ -251,8 +251,8 @@ gdtaddr:
.data
/* This is the gdt for GCC part of LinuxBIOS.
* It is different from the gdt in ROMCC/ASM part of LinuxBIOS
/* This is the gdt for GCC part of coreboot.
* It is different from the gdt in ROMCC/ASM part of coreboot
* which is defined in entry32.inc */
gdt:
/* selgdt 0, unused */

12
src/arch/i386/lib/console.c
View File

@ -19,19 +19,19 @@ static void __console_tx_byte(unsigned char byte)
#endif /* CONFIG_USE_PRINTK_IN_CAR */
#ifndef LINUXBIOS_EXTRA_VERSION
#define LINUXBIOS_EXTRA_VERSION ""
#ifndef COREBOOT_EXTRA_VERSION
#define COREBOOT_EXTRA_VERSION ""
#endif
static void console_init(void)
{
static const char console_test[] =
"\r\n\r\nLinuxBIOS-"
LINUXBIOS_VERSION
LINUXBIOS_EXTRA_VERSION
"\r\n\r\ncoreboot-"
COREBOOT_VERSION
COREBOOT_EXTRA_VERSION
" "
LINUXBIOS_BUILD
COREBOOT_BUILD
" starting...\r\n";
print_info(console_test);
}

4
src/arch/ppc/Config.lb
View File

@ -1,7 +1,7 @@
ldscript init/ldscript.lb
makerule linuxbios.rom
depends "linuxbios"
makerule coreboot.rom
depends "coreboot"
action "cp $< $@"
end

2
src/arch/ppc/boot/boot.c
View File

@ -29,7 +29,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
*/
flush_dcache();
/* On ppc we don't currently support loading over LinuxBIOS.
/* On ppc we don't currently support loading over coreboot.
* So ignore the buffer.
*/

32
src/arch/ppc/boot/linuxbios_table.c
View File

@ -104,16 +104,16 @@ void lb_strings(struct lb_header *header)
uint32_t tag;
const uint8_t *string;
} strings[] = {
{ LB_TAG_VERSION, linuxbios_version, },
{ LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
{ LB_TAG_BUILD, linuxbios_build, },
{ LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
{ LB_TAG_COMPILE_BY, linuxbios_compile_by, },
{ LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
{ LB_TAG_COMPILER, linuxbios_compiler, },
{ LB_TAG_LINKER, linuxbios_linker, },
{ LB_TAG_ASSEMBLER, linuxbios_assembler, },
{ LB_TAG_VERSION, coreboot_version, },
{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
{ LB_TAG_BUILD, coreboot_build, },
{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
{ LB_TAG_COMPILER, coreboot_compiler, },
{ LB_TAG_LINKER, coreboot_linker, },
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@ -183,7 +183,7 @@ unsigned long lb_table_fini(struct lb_header *head)
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
@ -297,8 +297,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
lb_cleanup_memory_ranges(mem);
}
/* Routines to extract part so the linuxBIOS table or
* information from the linuxBIOS table after we have written it.
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
@ -330,7 +330,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
return mem;
}
unsigned long write_linuxbios_table(
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
@ -363,9 +363,9 @@ unsigned long write_linuxbios_table(
/* Note:
* I assume that there is always memory at immediately after
* the low_table_end. This means that after I setup the linuxbios table.
* the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
* size of the linuxbios table.
* size of the coreboot table.
*/
/* Record our motheboard */

14
src/arch/ppc/boot/linuxbios_table.h
View File

@ -1,12 +1,12 @@
#ifndef LINUXBIOS_TABLE_H
#define LINUXBIOS_TABLE_H
#ifndef COREBOOT_TABLE_H
#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
struct mem_range;
/* This file holds function prototypes for building the linuxbios table. */
unsigned long write_linuxbios_table(
/* This file holds function prototypes for building the coreboot table. */
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@ -21,11 +21,11 @@ void lb_memory_range(struct lb_memory *mem,
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
/* Routines to extract part so the linuxBIOS table or information
* from the linuxBIOS table.
/* Routines to extract part so the coreboot table or information
* from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
#endif /* LINUXBIOS_TABLE_H */
#endif /* COREBOOT_TABLE_H */

4
src/arch/ppc/boot/tables.c
View File

@ -18,8 +18,8 @@ write_tables(void)
low_table_start = 0;
low_table_end = 16;
/* The linuxbios table must be in 0-4K or 960K-1M */
write_linuxbios_table(
/* The coreboot table must be in 0-4K or 960K-1M */
write_coreboot_table(
low_table_start, low_table_end,
rom_table_start, rom_table_end);

14
src/arch/ppc/init/ldscript.lb
View File

@ -5,7 +5,7 @@
* _RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table
*
* _ROMSTART : linuxbios text
* _ROMSTART : coreboot text
* : payload text
*
* _RAMBASE : address to copy payload
@ -26,7 +26,7 @@ OUTPUT_FORMAT("elf32-powerpc")
ENTRY(_start)
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
/*
@ -54,7 +54,7 @@ SECTIONS
}
/*
* Absolute location of LinuxBIOS initialization code in ROM.
* Absolute location of coreboot initialization code in ROM.
*/
. = _ROMSTART;
.rom . : {
@ -63,7 +63,7 @@ SECTIONS
*(.text);
*(.rom.data);
*(.rodata);
*(EXCLUDE_FILE(linuxbios_ram.rom) .data);
*(EXCLUDE_FILE(coreboot_ram.rom) .data);
. = ALIGN(16);
_erom = .;
}
@ -71,16 +71,16 @@ SECTIONS
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/*
* Ram is the LinuxBIOS code that runs from RAM.
* Ram is the coreboot code that runs from RAM.
*/
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}
/*
* Absolute location of where LinuxBIOS will be relocated in RAM.
* Absolute location of where coreboot will be relocated in RAM.
*/
_iseg = _RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);

22
src/boot/elfboot.c
View File

@ -9,7 +9,7 @@
#include <stdlib.h>
#include <string.h>
/* Maximum physical address we can use for the linuxBIOS bounce buffer.
/* Maximum physical address we can use for the coreboot bounce buffer.
*/
#ifndef MAX_ADDR
#define MAX_ADDR -1UL
@ -88,16 +88,16 @@ int verify_ip_checksum(
* a machine, and implementing general relocation is hard.
*
* The solution:
* - Allocate a buffer twice the size of the linuxBIOS image.
* - Anything that would overwrite linuxBIOS copy into the lower half of
* - Allocate a buffer twice the size of the coreboot image.
* - Anything that would overwrite coreboot copy into the lower half of
* the buffer.
* - After loading an ELF image copy linuxBIOS to the upper half of the
* - After loading an ELF image copy coreboot to the upper half of the
* buffer.
* - Then jump to the loaded image.
*
* Benefits:
* - Nearly arbitrary standalone executables can be loaded.
* - LinuxBIOS is preserved, so it can be returned to.
* - Coreboot is preserved, so it can be returned to.
* - The implementation is still relatively simple,
* and much simpler then the general case implemented in kexec.
*
@ -110,7 +110,7 @@ static unsigned long get_bounce_buffer(struct lb_memory *mem)
unsigned long buffer;
int i;
lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
/* Double linuxBIOS size so I have somewhere to place a copy to return to */
/* Double coreboot size so I have somewhere to place a copy to return to */
lb_size = lb_size + lb_size;
mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
buffer = 0;
@ -251,7 +251,7 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer,
static void relocate_segment(unsigned long buffer, struct segment *seg)
{
/* Modify all segments that want to load onto linuxBIOS
/* Modify all segments that want to load onto coreboot
* to load onto the bounce buffer instead.
*/
unsigned long lb_start = (unsigned long)&_ram_seg;
@ -264,7 +264,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
start = seg->s_addr;
middle = start + seg->s_filesz;
end = start + seg->s_memsz;
/* I don't conflict with linuxBIOS so get out of here */
/* I don't conflict with coreboot so get out of here */
if ((end <= lb_start) || (start >= lb_end))
return;
@ -272,7 +272,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
start, middle, end);
/* Slice off a piece at the beginning
* that doesn't conflict with linuxBIOS.
* that doesn't conflict with coreboot.
*/
if (start < lb_start) {
struct segment *new;
@ -311,7 +311,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
}
/* Slice off a piece at the end
* that doesn't conflict with linuxBIOS
* that doesn't conflict with coreboot
*/
if (end > lb_end) {
unsigned long len = lb_end - start;
@ -545,7 +545,7 @@ int elfload(struct lb_memory *mem,
struct verify_callback *cb_chain;
unsigned long bounce_buffer;
/* Find a bounce buffer so I can load to linuxBIOS's current location */
/* Find a bounce buffer so I can load to coreboot's current location */
bounce_buffer = get_bounce_buffer(mem);
if (!bounce_buffer) {
printk_err("Could not find a bounce buffer...\n");

2
src/boot/filo.c
View File

@ -2,7 +2,7 @@
* Copyright (C) 2003 by SONE Takeshi <ts1@tsn.or.jp> and others.
* This program is licensed under the terms of GNU General Public License.
*
* Modified for LinuxBIOS by Greg Watson <gwatson@lanl.gov>
* Modified for coreboot by Greg Watson <gwatson@lanl.gov>
*/
#include <console/console.h>

10
src/boot/hardwaremain.c
View File

@ -22,7 +22,7 @@ it with the version available from LANL.
/*
* C Bootstrap code for the LinuxBIOS
* C Bootstrap code for the coreboot
*/
@ -38,9 +38,9 @@ it with the version available from LANL.
#include <boot/elf.h>
/**
* @brief Main function of the DRAM part of LinuxBIOS.
* @brief Main function of the DRAM part of coreboot.
*
* LinuxBIOS is divided into Pre-DRAM part and DRAM part.
* Coreboot is divided into Pre-DRAM part and DRAM part.
*
*
* Device Enumeration:
@ -57,8 +57,8 @@ void hardwaremain(int boot_complete)
post_code(0x39);
printk_notice("LinuxBIOS-%s%s %s %s...\n",
linuxbios_version, linuxbios_extra_version, linuxbios_build,
printk_notice("coreboot-%s%s %s %s...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
post_code(0x40);

116
src/config/Config.lb
View File

@ -27,102 +27,102 @@ end
# action "perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
#end
makerule linuxbios.strip
depends "linuxbios"
action "$(OBJCOPY) -O binary linuxbios linuxbios.strip"
makerule coreboot.strip
depends "coreboot"
action "$(OBJCOPY) -O binary coreboot coreboot.strip"
end
makerule linuxbios.a
makerule coreboot.a
depends "$(OBJECTS)"
action "rm -f linuxbios.a"
action "ar cr linuxbios.a $(OBJECTS)"
action "rm -f coreboot.a"
action "ar cr coreboot.a $(OBJECTS)"
end
makerule linuxbios_ram.o
depends "$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
makerule coreboot_ram.o
depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
end
makerule linuxbios_ram
depends "linuxbios_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld linuxbios_ram.o"
action "$(CROSS_COMPILE)nm -n linuxbios_ram | sort > linuxbios_ram.map"
makerule coreboot_ram
depends "coreboot_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld coreboot_ram.o"
action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
end
##
## By default compress the part of linuxbios that runs from RAM
## By default compress the part of coreboot that runs from RAM
##
makedefine LINUXBIOS_RAM-$(CONFIG_COMPRESS):=linuxbios_ram.nrv2b
makedefine LINUXBIOS_RAM-$(CONFIG_UNCOMPRESSED):=linuxbios_ram.bin
makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b
makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
makerule linuxbios_ram.bin
depends "linuxbios_ram"
makerule coreboot_ram.bin
depends "coreboot_ram"
action "$(OBJCOPY) -O binary $< $@"
end
makerule linuxbios_ram.nrv2b
depends "linuxbios_ram.bin nrv2b"
makerule coreboot_ram.nrv2b
depends "coreboot_ram.bin nrv2b"
action "./nrv2b e $< $@"
end
makerule linuxbios_ram.rom
depends "$(LINUXBIOS_RAM-1)"
action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
makerule coreboot_ram.rom
depends "$(COREBOOT_RAM-1)"
action "cp $(COREBOOT_RAM-1) coreboot_ram.rom"
end
makedefine LINUXBIOS_APC:=
makedefine COREBOOT_APC:=
if CONFIG_AP_CODE_IN_CAR
#for ap code in cache
makerule linuxbios_apc.a
makerule coreboot_apc.a
depends "apc_auto.o"
action "rm -f linuxbios_apc.a"
action "ar cr linuxbios_apc.a apc_auto.o"
action "rm -f coreboot_apc.a"
action "ar cr coreboot_apc.a apc_auto.o"
end
makerule linuxbios_apc.o
depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)"
makerule coreboot_apc.o
depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
action "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
end
makerule linuxbios_apc
depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o"
action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map"
makerule coreboot_apc
depends "coreboot_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld coreboot_apc.o"
action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
end
##
## By default compress the part of linuxbios that runs from cache as ram
## By default compress the part of coreboot that runs from cache as ram
##
makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b
makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b
makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
makerule linuxbios_apc.bin
depends "linuxbios_apc"
makerule coreboot_apc.bin
depends "coreboot_apc"
action "$(OBJCOPY) -O binary $< $@"
end
makerule linuxbios_apc.nrv2b
depends "linuxbios_apc.bin nrv2b"
makerule coreboot_apc.nrv2b
depends "coreboot_apc.bin nrv2b"
action "./nrv2b e $< $@"
end
makerule linuxbios_apc.rom
depends "$(LINUXBIOS_APC-1)"
action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom"
makerule coreboot_apc.rom
depends "$(COREBOOT_APC-1)"
action "cp $(COREBOOT_APC-1) coreboot_apc.rom"
end
makedefine LINUXBIOS_APC:=linuxbios_apc.rom
makedefine COREBOOT_APC:=coreboot_apc.rom
end
makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
makerule linuxbios
depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
makerule coreboot
depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end
#makerule crt0.S
@ -158,14 +158,14 @@ makerule tags
depends "$(SOURCES)"
action "ctags $(SOURCES)"
end
makerule LinuxBIOSDoc.config
depends "$(TOP)/src/config/LinuxBIOSDoc.config"
action "cat $(TOP)/src/config/LinuxBIOSDoc.config > LinuxBIOSDoc.config"
action "echo 'INPUT=$(SOURCES)' >> LinuxBIOSDoc.config"
makerule corebootDoc.config
depends "$(TOP)/src/config/corebootDoc.config"
action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config"
action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config"
end
makerule documentation
depends "LinuxBIOSDoc.config"
action "doxygen LinuxBIOSDoc.config"
depends "corebootDoc.config"
action "doxygen corebootDoc.config"
end
makerule ./romcc
@ -204,12 +204,12 @@ object ./option_table.o
end
makerule clean
action "rm -f linuxbios.* *~"
action "rm -f linuxbios"
action "rm -f coreboot.* *~"
action "rm -f coreboot"
action "rm -f ldscript.ld"
action "rm -f a.out *.s *.l *.o *.E *.inc"
action "rm -f TAGS tags romcc*"
action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*"
action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S"
end

2
src/config/LinuxBIOSDoc.config
View File

@ -3,7 +3,7 @@
#---------------------------------------------------------------------------
# Project related configuration options
#---------------------------------------------------------------------------
PROJECT_NAME = LinuxBIOS
PROJECT_NAME = coreboot
PROJECT_NUMBER =
OUTPUT_DIRECTORY = .
CREATE_SUBDIRS = NO

44
src/config/Options.lb
View File

@ -1,6 +1,6 @@
#######################################################
#
# Main options file for LinuxBIOS
# Main options file for coreboot
#
# Each option used by a part must be defined in
# this file. The format for options is:
@ -96,62 +96,62 @@ define OBJCOPY
export always
comment "Objcopy command"
end
define LINUXBIOS_VERSION
define COREBOOT_VERSION
default "2.0.0"
export always
format "\"%s\""
comment "LinuxBIOS version"
comment "coreboot version"
end
define LINUXBIOS_EXTRA_VERSION
define COREBOOT_EXTRA_VERSION
default ""
export used
format "\"%s\""
comment "LinuxBIOS extra version"
comment "coreboot extra version"
end
define LINUXBIOS_BUILD
define COREBOOT_BUILD
default "$(shell date)"
export always
format "\"%s\""
comment "Build date"
end
define LINUXBIOS_COMPILE_TIME
define COREBOOT_COMPILE_TIME
default "$(shell date +%T)"
export always
format "\"%s\""
comment "Build time"
end
define LINUXBIOS_COMPILE_BY
define COREBOOT_COMPILE_BY
default "$(shell whoami)"
export always
format "\"%s\""
comment "Who build this image"
end
define LINUXBIOS_COMPILE_HOST
define COREBOOT_COMPILE_HOST
default "$(shell hostname)"
export always
format "\"%s\""
comment "Build host"
end
define LINUXBIOS_COMPILE_DOMAIN
define COREBOOT_COMPILE_DOMAIN
default "$(shell dnsdomainname)"
export always
format "\"%s\""
comment "Build domain name"
end
define LINUXBIOS_COMPILER
define COREBOOT_COMPILER
default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
export always
format "\"%s\""
comment "Build compiler"
end
define LINUXBIOS_LINKER
define COREBOOT_LINKER
default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
export always
format "\"%s\""
comment "Build linker"
end
define LINUXBIOS_ASSEMBLER
define COREBOOT_ASSEMBLER
default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
export always
format "\"%s\""
@ -242,13 +242,13 @@ define _ROMBASE
default {PAYLOAD_SIZE}
format "0x%x"
export always
comment "Base address of LinuxBIOS in ROM"
comment "Base address of coreboot in ROM"
end
define _ROMSTART
default none
format "0x%x"
export used
comment "Start address of LinuxBIOS in ROM"
comment "Start address of coreboot in ROM"
end
define _RESET
default {_ROMBASE}
@ -278,13 +278,13 @@ define _RAMBASE
default none
format "0x%x"
export always
comment "Base address of LinuxBIOS in RAM"
comment "Base address of coreboot in RAM"
end
define _RAMSTART
default none
format "0x%x"
export used
comment "Start address of LinuxBIOS in RAM"
comment "Start address of coreboot in RAM"
end
define USE_DCACHE_RAM
default 0
@ -317,7 +317,7 @@ end
define CONFIG_AP_CODE_IN_CAR
default 0
export always
comment "will copy linuxbios_apc to AP cache ane execute in AP"
comment "will copy coreboot_apc to AP cache ane execute in AP"
end
define MEM_TRAIN_SEQ
default 0
@ -333,13 +333,13 @@ define XIP_ROM_BASE
default 0
format "0x%x"
export used
comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
comment "Start address of area to cache during coreboot execution directly from ROM"
end
define XIP_ROM_SIZE
default 0
format "0x%x"
export used
comment "Size of area to cache during LinuxBIOS execution directly from ROM"
comment "Size of area to cache during coreboot execution directly from ROM"
end
define CONFIG_COMPRESS
default 1
@ -377,13 +377,13 @@ define LB_CKS_RANGE_START
default 49
format "%d"
export always
comment "First CMOS byte to use for LinuxBIOS options"
comment "First CMOS byte to use for coreboot options"
end
define LB_CKS_RANGE_END
default 125
format "%d"
export always
comment "Last CMOS byte to use for LinuxBIOS options"
comment "Last CMOS byte to use for coreboot options"
end
define LB_CKS_LOC
default 126

2
src/config/doxyscript.base
View File

@ -16,7 +16,7 @@
# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
# by quotes) that should identify the project.
PROJECT_NAME = "LinuxBIOS"
PROJECT_NAME = "coreboot"
# The PROJECT_NUMBER tag can be used to enter a project or revision number.
# This could be handy for archiving the generated documentation or

6
src/config/linuxbios_apc.ld
View File

@ -15,7 +15,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2006.05 yhlu tailed it to use it for AP code in cache
*/
/*
@ -85,12 +85,12 @@ SECTIONS
}
_eheap = .;
/* The ram segment
* This is all address of the memory resident copy of linuxBIOS.
* This is all address of the memory resident copy of coreboot.
*/
_ram_seg = _text;
_eram_seg = _eheap;
_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "linuxbios_apc is too big");
_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
/DISCARD/ : {
*(.comment)

6
src/config/linuxbios_ram.ld
View File

@ -15,7 +15,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
*/
/*
* We use ELF as output format. So that we can
@ -57,7 +57,7 @@ SECTIONS
/*
* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
* This breaksthe linuxbios.strip target.
* This breaks the coreboot.strip target.
*/
. = ALIGN(4);
@ -104,7 +104,7 @@ SECTIONS
}
_eheap = .;
/* The ram segment
* This is all address of the memory resident copy of linuxBIOS.
* This is all address of the memory resident copy of coreboot.
*/
_ram_seg = _text;
_eram_seg = _eheap;

2
src/console/btext_console.c
View File

@ -3,7 +3,7 @@
*
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
*
* move to LinuxBIOS by LYH yhlu@tyan.com
* move to coreboot by LYH yhlu@tyan.com
*/
#if 0

8
src/cpu/amd/car/copy_and_run.c
View File

@ -23,7 +23,7 @@ static void copy_and_run(void)
uint8_t *src, *dst;
unsigned long ilen, olen;
print_debug("Copying LinuxBIOS to RAM.\r\n");
print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
@ -55,7 +55,7 @@ static void copy_and_run(void)
print_debug_cp_run("linxbios_ram.bin length = ", olen);
print_debug("Jumping to LinuxBIOS.\r\n");
print_debug("Jumping to coreboot.\r\n");
__asm__ volatile (
"xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
@ -73,7 +73,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
uint8_t *src, *dst;
unsigned long ilen, olen;
// print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
// print_debug("Copying coreboot AP code to CAR.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
@ -105,7 +105,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
// print_debug_cp_run("linxbios_apc.bin length = ", olen);
// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
// print_debug("Jumping to coreboot AP code in CAR.\r\n");
__asm__ volatile (
"movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */

2
src/cpu/amd/car/disable_cache_as_ram.c
View File

@ -21,7 +21,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
"wrmsr\n\t"
#endif
/* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
"movl $0xC0010010, %ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t"

2
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -104,7 +104,7 @@ static void post_cache_as_ram(void)
// wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
#endif
/*copy and execute linuxbios_ram */
/*copy and execute coreboot_ram */
copy_and_run();
/* We will not return */

8
src/cpu/amd/model_gx2/vsmsetup.c
View File

@ -10,7 +10,7 @@
/* what a mess this uncompress thing is. I am not at all happy about how this
* was done, but can't fix it yet. RGM
*/
#warning "Fix the uncompress once linuxbios knows how to do it"
#warning "Fix the uncompress once coreboot knows how to do it"
#include "../lib/nrv2b.c"
/* vsmsetup.c derived from vgabios.c. Derived from: */
@ -71,7 +71,7 @@
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
without reliance on other parts of core Linuxbios
without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
@ -320,10 +320,10 @@ struct realidt {
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
// second, since this only ever runs as part of linuxbios,
// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
// more complex code in linuxbios itself. This helps a lot as we don't
// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)

8
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
@ -213,7 +213,7 @@ __main:
cld /* clear direction flag */
/* copy linuxBIOS from it's initial load location to
/* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
@ -363,8 +363,8 @@ crt_console_tx_string:
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n"
str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
str_copying_to_ram: .string "Copying coreboot to ram.\r\n"
str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */

6
src/cpu/amd/model_lx/vsmsetup.c
View File

@ -75,7 +75,7 @@
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
without reliance on other parts of core Linuxbios
without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
@ -341,10 +341,10 @@ struct realidt {
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
// second, since this only ever runs as part of linuxbios,
// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
// more complex code in linuxbios itself. This helps a lot as we don't
// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)

2
src/cpu/amd/sc520/sc520.c
View File

@ -157,7 +157,7 @@ static void pci_domain_set_resources(device_t dev)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future linuxbios
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)

2
src/cpu/emulation/qemu-i386/northbridge.c
View File

@ -86,7 +86,7 @@ static void pci_domain_set_resources(device_t dev)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future linuxbios
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)

2
src/cpu/ppc/mpc74xx/Config.lb
View File

@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
## Use cache ram for initial setup
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 32Kb
default DCACHE_RAM_SIZE=0x8000

4
src/cpu/ppc/mpc74xx/mpc74xx.inc
View File

@ -19,7 +19,7 @@
/*
* The aim of this code is to bring the machine from power-on to the point
* where we can jump to the the main LinuxBIOS entry point hardwaremain()
* where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@ -79,7 +79,7 @@
isync
/*
* Clear segment registers (LinuxBIOS doesn't use these)
* Clear segment registers (coreboot doesn't use these)
*/
mtsr 0, r0
isync

2
src/cpu/ppc/ppc4xx/Config.lb
View File

@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
## PPC4XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384

2
src/cpu/ppc/ppc7xx/Config.lb
View File

@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
## PPC7XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384

4
src/cpu/ppc/ppc7xx/ppc7xx.inc
View File

@ -19,7 +19,7 @@
/*
* The aim of this code is to bring the machine from power-on to the point
* where we can jump to the the main LinuxBIOS entry point hardwaremain()
* where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@ -72,7 +72,7 @@
isync
/*
* Clear segment registers (LinuxBIOS doesn't use these)
* Clear segment registers (coreboot doesn't use these)
*/
li r3, 15
1: mtsrin r3, r0

6
src/cpu/x86/32bit/entry32.inc
View File

@ -1,4 +1,4 @@
/* For starting linuxBIOS in protected mode */
/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
@ -8,8 +8,8 @@
.align 4
.globl gdtptr
/* This is the gdt for ROMCC/ASM part of LinuxBIOS.
* It is different from the gdt in GCC part of LinuxBIOS
/* This is the gdt for ROMCC/ASM part of coreboot.
* It is different from the gdt in GCC part of coreboot
* which is defined in c_start.S */
gdt:
gdtptr:

4
src/cpu/x86/car/copy_and_run.c
View File

@ -15,7 +15,7 @@ static void copy_and_run(unsigned cpu_reset)
unsigned long dst_len;
unsigned long ilen, olen;
print_debug("Copying LinuxBIOS to RAM.\r\n");
print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
@ -53,7 +53,7 @@ static void copy_and_run(unsigned cpu_reset)
#else
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
#endif
print_debug("Jumping to LinuxBIOS.\r\n");
print_debug("Jumping to coreboot.\r\n");
if(cpu_reset == 1 ) {
__asm__ volatile (

4
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -1,5 +1,5 @@
/*
2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
2005.12 yhlu add coreboot_ram cross the vga font buffer handling
2005.12 yhlu add _RAMBASE above 1M support for SMP
*/
@ -191,7 +191,7 @@ static int lapic_start_cpu(unsigned long apicid)
return 1;
}
/* Number of cpus that are currently running in linuxbios */
/* Number of cpus that are currently running in coreboot */
static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack.

2
src/cpu/x86/pae/pgtbl.c
View File

@ -1,5 +1,5 @@
/*
2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
2005.12 yhlu add coreboot_ram cross the vga font buffer handling
*/
#include <console/console.h>

2
src/devices/emulator/x86emu/sys.c
View File

@ -45,7 +45,7 @@
#include <x86emu/regs.h>
#include "debug.h"
#include "prim_ops.h"
#ifdef LINUXBIOS_VERSION
#ifdef COREBOOT_VERSION
#include "arch/io.h"
#else
#include <sys/io.h>

2
src/drivers/ati/ragexl/xlinit.c
View File

@ -7,7 +7,7 @@
* stevel@mvista.com or source@mvista.com
* Copyright (C) 2004 Tyan Computer.
* Auther: Yinghai Lu yhlu@tyan.com
* move to LinuxBIOS
* move to coreboot
* This code is distributed without warranty under the GPL v2 (see COPYING) *
*/
#include <delay.h>

8
src/drivers/pci/onboard/onboard.c
View File

@ -24,8 +24,8 @@
in your MB targets Config.lb, afer romimage "normal"
3. create you vgabios.bin under normal bios and put that in dir that targets Config residues.
# dd if=/dev/mem of=atix.rom skip=1536 count=96
4. after build linuxbios.rom
# cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > linuxbios.rom
4. after build coreboot.rom
# cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
or use nsxv to build you image
# time ./nsxv s2850
@ -52,8 +52,8 @@ eval make &> "$LBROOT/x_m.txt"
tail -n 15 "$LBROOT/x_m.txt"
exit
fi
cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > "$LBROOT/rom/"$MBMODEL"_linuxbios.rom"
cp -f "$LBROOT/rom/"$MBMODEL"_linuxbios.rom" /home/yhlu/
cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
date

2
src/include/boot/elf.h
View File

@ -394,7 +394,7 @@ extern void jmp_to_elf_entry(void *entry, unsigned long buffer);
struct lb_memory;
extern int elfboot(struct lb_memory *mem);
#define FIRMWARE_TYPE "LinuxBIOS"
#define FIRMWARE_TYPE "coreboot"
#define BOOTLOADER "elfboot"
#define BOOTLOADER_VERSION "1.3"

14
src/include/boot/linuxbios_tables.h
View File

@ -1,9 +1,9 @@
#ifndef LINUXBIOS_TABLES_H
#define LINUXBIOS_TABLES_H
#ifndef COREBOOT_TABLES_H
#define COREBOOT_TABLES_H
#include <stdint.h>
/* The linuxbios table information is for conveying information
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as quering the hardware directly.
@ -31,12 +31,12 @@
* table entries and be backwards compatible, but it is not required.
*/
/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the LinuxBIOS table is dumped on a
/* Since coreboot is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a uint64_t would be aligned to 64bit boundaries,
* breaking the table format.
*
* lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit
* lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
@ -213,4 +213,4 @@ struct cmos_checksum {
#endif /* LINUXBIOS_TABLES_H */
#endif /* COREBOOT_TABLES_H */

2
src/include/console/btext.h
View File

@ -4,7 +4,7 @@
*
* Written by Benjamin Herrenschmidt.
*
* Move to LinuxBIOS by LYH yhlu@tyan.com
* Move to coreboot by LYH yhlu@tyan.com
*
*/

2
src/include/device/pci_ids.h
View File

@ -2507,7 +2507,7 @@
#define PCI_DEVICE_ID_SIS_SIS968_PCIE 0x000a /* D6F0,D7F0 */
#define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */
/* OLD USAGE FOR LINUXBIOS */
/* OLD USAGE FOR COREBOOT */
#define PCI_VENDOR_ID_ACER 0x10b9
#define PCI_DEVICE_ID_ACER_M1535D 0x1533

24
src/include/version.h
View File

@ -5,18 +5,18 @@
extern const char mainboard_vendor[];
extern const char mainboard_part_number[];
/* LinuxBIOS Version */
extern const char linuxbios_version[];
extern const char linuxbios_extra_version[];
extern const char linuxbios_build[];
/* coreboot Version */
extern const char coreboot_version[];
extern const char coreboot_extra_version[];
extern const char coreboot_build[];
/* When LinuxBIOS was compiled */
extern const char linuxbios_compile_time[];
extern const char linuxbios_compile_by[];
extern const char linuxbios_compile_host[];
extern const char linuxbios_compile_domain[];
extern const char linuxbios_compiler[];
extern const char linuxbios_linker[];
extern const char linuxbios_assembler[];
/* When coreboot was compiled */
extern const char coreboot_compile_time[];
extern const char coreboot_compile_by[];
extern const char coreboot_compile_host[];
extern const char coreboot_compile_domain[];
extern const char coreboot_compiler[];
extern const char coreboot_linker[];
extern const char coreboot_assembler[];
#endif /* VERSION_H */

2
src/include/x86emu/x86emu.h
View File

@ -43,7 +43,7 @@
#define __X86EMU_X86EMU_H
/* FIXME: undefine printk for the moment */
#ifdef LINUXBIOS_VERSION
#ifdef COREBOOT_VERSION
#include "console/console.h"
#define printk printk_debug
#else

2
src/lib/lzma.c
View File

@ -1,6 +1,6 @@
/*
LinuxBIOS interface to memory-saving variant of LZMA decoder
Coreboot interface to memory-saving variant of LZMA decoder
(C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL

2
src/lib/usbdebug_direct.c
View File

@ -5,7 +5,7 @@
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* 2006.12.10 yhlu moved it to LinuxBIOS and use struct instead
* 2006.12.10 yhlu moved it to corbeoot and use struct instead
*/
#ifndef __ROMCC__
#include <console/console.h>

56
src/lib/version.c
View File

@ -7,52 +7,52 @@
#error MAINBOARD_PART_NUMBER not defined
#endif
#ifndef LINUXBIOS_VERSION
#error LINUXBIOS_VERSION not defined
#ifndef COREBOOT_VERSION
#error COREBOOT_VERSION not defined
#endif
#ifndef LINUXBIOS_BUILD
#error LINUXBIOS_BUILD not defined
#ifndef COREBOOT_BUILD
#error COREBOOT_BUILD not defined
#endif
#ifndef LINUXBIOS_COMPILE_TIME
#error LINUXBIOS_COMPILE_TIME not defined
#ifndef COREBOOT_COMPILE_TIME
#error COREBOOT_COMPILE_TIME not defined
#endif
#ifndef LINUXBIOS_COMPILE_BY
#error LINUXBIOS_COMPILE_BY not defined
#ifndef COREBOOT_COMPILE_BY
#error COREBOOT_COMPILE_BY not defined
#endif
#ifndef LINUXBIOS_COMPILE_HOST
#error LINUXBIOS_COMPILE_HOST not defined
#ifndef COREBOOT_COMPILE_HOST
#error COREBOOT_COMPILE_HOST not defined
#endif
#ifndef LINUXBIOS_COMPILER
#error LINUXBIOS_COMPILER not defined
#ifndef COREBOOT_COMPILER
#error COREBOOT_COMPILER not defined
#endif
#ifndef LINUXBIOS_LINKER
#error LINUXBIOS_LINKER not defined
#ifndef COREBOOT_LINKER
#error COREBOOT_LINKER not defined
#endif
#ifndef LINUXBIOS_ASSEMBLER
#error LINUXBIOS_ASSEMBLER not defined
#ifndef COREBOOT_ASSEMBLER
#error COREBOOT_ASSEMBLER not defined
#endif
#ifndef LINUXBIOS_EXTRA_VERSION
#define LINUXBIOS_EXTRA_VERSION ""
#ifndef COREBOOT_EXTRA_VERSION
#define COREBOOT_EXTRA_VERSION ""
#endif
const char mainboard_vendor[] = MAINBOARD_VENDOR;
const char mainboard_part_number[] = MAINBOARD_PART_NUMBER;
const char linuxbios_version[] = LINUXBIOS_VERSION;
const char linuxbios_extra_version[] = LINUXBIOS_EXTRA_VERSION;
const char linuxbios_build[] = LINUXBIOS_BUILD;
const char coreboot_version[] = COREBOOT_VERSION;
const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION;
const char coreboot_build[] = COREBOOT_BUILD;
const char linuxbios_compile_time[] = LINUXBIOS_COMPILE_TIME;
const char linuxbios_compile_by[] = LINUXBIOS_COMPILE_BY;
const char linuxbios_compile_host[] = LINUXBIOS_COMPILE_HOST;
const char linuxbios_compile_domain[] = LINUXBIOS_COMPILE_DOMAIN;
const char linuxbios_compiler[] = LINUXBIOS_COMPILER;
const char linuxbios_linker[] = LINUXBIOS_LINKER;
const char linuxbios_assembler[] = LINUXBIOS_ASSEMBLER;
const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME;
const char coreboot_compile_by[] = COREBOOT_COMPILE_BY;
const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST;
const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN;
const char coreboot_compiler[] = COREBOOT_COMPILER;
const char coreboot_linker[] = COREBOOT_LINKER;
const char coreboot_assembler[] = COREBOOT_ASSEMBLER;

2
src/mainboard/a-trend/atc-6220/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

2
src/mainboard/advantech/pcm-5820/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

14
src/mainboard/agami/aruma/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -145,7 +145,7 @@ else
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
@ -163,7 +163,7 @@ if USE_DCACHE_RAM
end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -193,7 +193,7 @@ if USE_DCACHE_RAM
end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/agami/aruma/Options.lb
View File

@ -37,7 +37,7 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
@ -140,7 +140,7 @@ default ACPI_SSDTX_NUM=3
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -196,10 +196,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@ -218,7 +218,7 @@ default HEAP_SIZE=0x8000
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@ -262,7 +262,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
@ -275,7 +275,7 @@ default TTYS0_LCS=0x3
## SPEW 9 Way too many details
## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb
## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging

4
src/mainboard/agami/aruma/acpi_tables_static.c
View File

@ -83,7 +83,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* The next two tables are used by our DSDT and are freely defined
* here. This construct is used because the bus numbers containing
* the 8131 bridges may vary so that we need to pass LinuxBIOS
* the 8131 bridges may vary so that we need to pass coreboot
* knowledge into the DSDT
*/
typedef struct lnxc_busses {
@ -96,7 +96,7 @@ typedef struct acpi_lnxb {
acpi_lnxb_busses_t busses[5];
} acpi_lnxb_t;
/* special linuxbios acpi table */
/* special coreboot acpi table */
void acpi_create_lnxb(acpi_lnxb_t *lnxb)
{
device_t dev;

14
src/mainboard/amd/db800/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,19 +12,19 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -62,7 +62,7 @@ end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -70,7 +70,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -90,7 +90,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/amd/db800/Options.lb
View File

@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -92,10 +92,10 @@ default IRQ_SLOT_COUNT=4
default HAVE_OPTION_TABLE=0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@ -158,7 +158,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/amd/norwich/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,19 +12,19 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -64,7 +64,7 @@ end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -72,7 +72,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -92,7 +92,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/amd/norwich/Options.lb
View File

@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -92,10 +92,10 @@ default IRQ_SLOT_COUNT=6
default HAVE_OPTION_TABLE=0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@ -158,7 +158,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/amd/rumba/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -70,7 +70,7 @@ makerule ./auto.inc
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/amd/rumba/Options.lb
View File

@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -82,10 +82,10 @@ default IRQ_SLOT_COUNT=2
default HAVE_OPTION_TABLE=0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@ -141,7 +141,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/amd/serengeti_cheetah/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
@ -17,18 +17,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -154,7 +154,7 @@ else
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
@ -181,7 +181,7 @@ if USE_DCACHE_RAM
end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -215,7 +215,7 @@ if USE_DCACHE_RAM
end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/amd/serengeti_cheetah/Options.lb
View File

@ -40,7 +40,7 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@ -122,7 +122,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@ -149,7 +149,7 @@ default ACPI_SSDTX_NUM=1
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -237,10 +237,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@ -259,7 +259,7 @@ default HEAP_SIZE=0x8000
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
@ -309,7 +309,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

8
src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
View File

@ -1,7 +1,7 @@
At this time, For acpi support We got
1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
4. Chipset support: amd8111, amd8132
The developers need to change for different MB
@ -11,7 +11,7 @@ Change dx/dsdt_lb.dsl, according to MB layout
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
Change acpi_tables.c
sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now.
sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic

14
src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
View File

@ -19,7 +19,7 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
@ -36,18 +36,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -163,7 +163,7 @@ else
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
@ -190,7 +190,7 @@ if USE_DCACHE_RAM
end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -225,7 +225,7 @@ if USE_DCACHE_RAM
end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
View File

@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@ -147,7 +147,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@ -174,7 +174,7 @@ default ACPI_SSDTX_NUM=31
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -261,10 +261,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@ -283,7 +283,7 @@ default HEAP_SIZE=0xc0000
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00200000
@ -334,7 +334,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/arima/hdama/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -91,7 +91,7 @@ end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@ -111,7 +111,7 @@ if USE_DCACHE_RAM
end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -141,7 +141,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/arima/hdama/Options.lb
View File

@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@ -82,7 +82,7 @@ default FALLBACK_SIZE=0x40000
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@ -104,7 +104,7 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -145,10 +145,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@ -167,7 +167,7 @@ default HEAP_SIZE=0x4000
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@ -216,7 +216,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/artecgroup/dbe61/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -60,7 +60,7 @@ end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -68,7 +68,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -88,7 +88,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/artecgroup/dbe61/Options.lb
View File

@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -93,10 +93,10 @@ default IRQ_SLOT_COUNT=3
default HAVE_OPTION_TABLE=0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@ -159,7 +159,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

8
src/mainboard/artecgroup/dbe61/realmode/vgabios.c
View File

@ -66,7 +66,7 @@
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
without reliance on other parts of core Linuxbios
without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
@ -442,10 +442,10 @@ struct realidt {
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
// second, since this only ever runs as part of linuxbios,
// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
// more complex code in linuxbios itself. This helps a lot as we don't
// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler_vga(void)
@ -921,7 +921,7 @@ static void vga_init(device_t dev)
pci_dev_init(dev);
// code to make vga init run in real mode - does work but against the current Linuxbios philosophy
// code to make vga init run in real mode - does work but against the current coreboot philosophy
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
printk_debug("DO THE VGA BIOS\n");

14
src/mainboard/asi/mb_5blmp/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -71,7 +71,7 @@ makerule ./auto.inc
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -79,7 +79,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -99,7 +99,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/asi/mb_5blmp/Options.lb
View File

@ -7,7 +7,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -57,7 +57,7 @@ default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -78,10 +78,10 @@ default IRQ_SLOT_COUNT=5 # TODO?
# default HAVE_OPTION_TABLE=0
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
@ -137,7 +137,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/asus/a8n_e/Config.lb
View File

@ -23,7 +23,7 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
@ -39,18 +39,18 @@ else
end
##
## Compute the start location and size size of the LinuxBIOS bootloader.
## Compute the start location and size size of the coreboot bootloader.
##
default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of LinuxBIOS will start in the boot ROM.
## Compute where this copy of coreboot will start in the boot ROM.
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can be cached to speed up LinuxBIOS
## Compute a range of ROM that can be cached to speed up coreboot
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
@ -106,7 +106,7 @@ if USE_DCACHE_RAM
end
##
## Build our 16 bit and 32 bit LinuxBIOS entry code.
## Build our 16 bit and 32 bit coreboot entry code.
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -130,7 +130,7 @@ if USE_DCACHE_RAM
end
##
## Build our reset vector (this is where LinuxBIOS is entered).
## Build our reset vector (this is where coreboot is entered).
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -186,7 +186,7 @@ end
###
### This is the early phase of LinuxBIOS startup.
### This is the early phase of coreboot startup.
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/asus/a8n_e/Options.lb
View File

@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
@ -127,7 +127,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@ -149,7 +149,7 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -223,10 +223,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = (64*1024)
#65536
@ -247,7 +247,7 @@ default HEAP_SIZE=0x4000
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@ -296,7 +296,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

14
src/mainboard/asus/a8v-e_se/Config.lb
View File

@ -23,7 +23,7 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -35,19 +35,19 @@
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -97,7 +97,7 @@ if USE_DCACHE_RAM
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
@ -122,7 +122,7 @@ end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
@ -141,7 +141,7 @@ if USE_DCACHE_RAM
end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

14
src/mainboard/asus/a8v-e_se/Options.lb
View File

@ -56,7 +56,7 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
@ -121,7 +121,7 @@ default FALLBACK_SIZE=256 * 1024
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@ -143,7 +143,7 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=0
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@ -217,10 +217,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
##
@ -242,7 +242,7 @@ default HEAP_SIZE=256 * 1024
##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## LinuxBIOS C code runs at this location in RAM
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@ -291,7 +291,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

2
src/mainboard/asus/mew-am/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

14
src/mainboard/asus/mew-vm/Config.lb
View File

@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@ -70,7 +70,7 @@ makerule ./auto.inc
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###

10
src/mainboard/asus/mew-vm/Options.lb
View File

@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
##
## Build code to reset the motherboard from linuxBIOS
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET = 0
@ -79,10 +79,10 @@ default HAVE_OPTION_TABLE = 0
default CONFIG_IDE = 1
###
### LinuxBIOS layout values
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@ -138,7 +138,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
### Select the linuxBIOS loglevel
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately

2
src/mainboard/asus/p2b-f/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

2
src/mainboard/asus/p2b/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

2
src/mainboard/asus/p3b-f/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

2
src/mainboard/axus/tc320/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

2
src/mainboard/axus/tc320/irq_tables.c
View File

@ -24,7 +24,7 @@
* It was not possible to read back the PIRQ table. There was no BIOS to ask
* for it, only a bootloader for an embedded OS.
* But with the method described here:
* http://linuxbios.org/Creating_Valid_IRQ_Tables
* http://coreboot.org/Creating_Valid_IRQ_Tables
* it was possible to detect the physical IRQ routing on this board.
*
* This is the physical routing on this board:

2
src/mainboard/azza/pt-6ibd/Options.lb
View File

@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE

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