mb/google/geralt: Configure GPIOs

Configure ChromeOS specific GPIOs:
- Open-drain pins to high-z mode:
  GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL.
- GPO mode:
  GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE.

This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/geralt/bootblock.c

@@ -13,5 +13,6 @@ void bootblock_mainboard_init(void)
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
+	setup_chromeos_gpios();
 	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
 }

src/mainboard/google/geralt/chromeos.c

@@ -7,9 +7,27 @@
 
 #include "gpio.h"
 
+void setup_chromeos_gpios(void)
+{
+	/* Set up open-drain pins */
+	gpio_input(GPIO_EC_AP_INT_ODL);
+	gpio_input(GPIO_GSC_AP_INT_ODL);
+	gpio_input(GPIO_AP_WP_ODL);
+
+	/* Set up GPOs */
+	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
+	gpio_output(GPIO_EN_SPKR, 0);
+	gpio_output(GPIO_XHCI_INIT_DONE, 0);
+}
+
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	/* TODO: add Chrome specific gpios */
+	struct lb_gpio chromeos_gpios[] = {
+		{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
+		{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
+		{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
 int tis_plat_irq_status(void)

src/mainboard/google/geralt/gpio.h

@@ -6,7 +6,12 @@
 #include <soc/gpio.h>
 
 #define GPIO_AP_EC_WARM_RST_REQ	GPIO(DPI_HSYNC)
+#define GPIO_AP_WP_ODL		GPIO(GPIO15)
+#define GPIO_BEEP_ON_OD		GPIO(I2SIN_WS)
+#define GPIO_EC_AP_INT_ODL	GPIO(DPI_DE)
+#define GPIO_EN_SPKR		GPIO(I2SIN_D2)
 #define GPIO_GSC_AP_INT_ODL	GPIO(GPIO00)
+#define GPIO_XHCI_INIT_DONE	GPIO(DPI_CK)
 
 void setup_chromeos_gpios(void);