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soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment 

Add UPD parameter for eDP power sequence adjustment.

The edp_panel_t9_ms parameter is set for bloff to varybloff.

BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2023-04-26 19:48:05 +08:00 committed by Martin L Roth
parent 78790c872c
commit f927026536
2 changed files with 3 additions and 0 deletions
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2
src/soc/amd/mendocino/chip.h
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@ -179,6 +179,8 @@ struct soc_amd_mendocino_config {
/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
uint8_t edp_panel_t8_ms;
/* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */
uint8_t edp_panel_t9_ms;
};

1
src/soc/amd/mendocino/fsp_m_params.c
View File

@ -171,6 +171,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms;
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);