soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -179,6 +179,8 @@ struct soc_amd_mendocino_config {
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/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
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/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
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uint8_t edp_panel_t8_ms;
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uint8_t edp_panel_t8_ms;
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/* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */
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uint8_t edp_panel_t9_ms;
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};
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};
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@ -171,6 +171,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
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mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
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mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
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mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
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mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms;
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fsp_fill_pcie_ddi_descriptors(mcfg);
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fsp_fill_pcie_ddi_descriptors(mcfg);
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fsp_assign_ioapic_upds(mcfg);
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fsp_assign_ioapic_upds(mcfg);
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