mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLAN
Pujjo support WLAN device, enable PCIe port 4 for WLAN device BUG=b:239899932 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,6 +13,7 @@ chip soc/intel/alderlake
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC Camera
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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# Configure external V1P05/Vnn/VnnSx Rails
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@ -228,6 +229,18 @@ chip soc/intel/alderlake
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device i2c 0x2c on end
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end
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end
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device ref pcie_rp4 on
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# PCIe 4 WLAN
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW1_03"
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device pci 00.0 on end
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end
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end
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device ref pcie_rp7 on
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# Enable SD Card PCIe 7 using clk 3
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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@ -314,6 +327,13 @@ chip soc/intel/alderlake
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""CNVi Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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