Arrange CBMEM table entries' IDs alphanumerically
This is a no-op change just sorting the CBMEM entries' definitions for
easy look up and comparison.
BRANCH=storm
BUG=none
TEST=Booted a storm device, observed the expected CBMEM entries
present in the console output.
Change-Id: I26365285f20ecb256918277b60e178cd61dc8213
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f140fd8d85ded30d1b89f5d4c64f8b9f31d6b27b
Original-Change-Id: Ibcd4f184ef1bade10ad677384f61243da7e3c713
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9810
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This commit is contained in:
Vadim Bendebury
Patrick Georgi
parent
dfd441d1a5
commit
f92edfe59c
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@ -42,43 +42,43 @@
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#define CBMEM_RESUME_BACKUP 0x614
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#define CBMEM_FSP_HOB_PTR 0x614
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#define CBMEM_ID_FREESPACE 0x46524545
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#define CBMEM_ID_GDT 0x4c474454
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#define CBMEM_ID_ACPI 0x41435049
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#define CBMEM_ID_ACPI_GNVS 0x474e5653
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#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
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#define CBMEM_ID_IGD_OPREGION 0x4f444749
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#define CBMEM_ID_AGESA_RUNTIME 0x41474553
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#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
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#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
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#define CBMEM_ID_CBTABLE 0x43425442
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#define CBMEM_ID_PIRQ 0x49525154
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#define CBMEM_ID_MPTABLE 0x534d5054
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#define CBMEM_ID_RESUME 0x5245534d
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#define CBMEM_ID_RESUME_SCRATCH 0x52455343
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#define CBMEM_ID_SMBIOS 0x534d4254
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#define CBMEM_ID_TIMESTAMP 0x54494d45
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#define CBMEM_ID_MRCDATA 0x4d524344
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#define CBMEM_ID_CONSOLE 0x434f4e53
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#define CBMEM_ID_ELOG 0x454c4f47
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#define CBMEM_ID_COVERAGE 0x47434f56
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#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
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#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
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#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
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#define CBMEM_ID_ELOG 0x454c4f47
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#define CBMEM_ID_FREESPACE 0x46524545
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#define CBMEM_ID_GDT 0x4c474454
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#define CBMEM_ID_HOB_POINTER 0x484f4221
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#define CBMEM_ID_IGD_OPREGION 0x4f444749
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#define CBMEM_ID_MEMINFO 0x494D454D
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#define CBMEM_ID_MPTABLE 0x534d5054
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#define CBMEM_ID_MRCDATA 0x4d524344
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#define CBMEM_ID_NONE 0x00000000
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#define CBMEM_ID_PIRQ 0x49525154
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#define CBMEM_ID_POWER_STATE 0x50535454
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#define CBMEM_ID_RAM_OOPS 0x05430095
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#define CBMEM_ID_RAMSTAGE 0x9a357a9e
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#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
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#define CBMEM_ID_ROOT 0xff4007ff
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#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
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#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
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#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
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#define CBMEM_ID_REFCODE 0x04efc0de
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#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
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#define CBMEM_ID_POWER_STATE 0x50535454
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#define CBMEM_ID_RESUME 0x5245534d
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#define CBMEM_ID_RESUME_SCRATCH 0x52455343
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#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
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#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
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#define CBMEM_ID_ROOT 0xff4007ff
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#define CBMEM_ID_SMBIOS 0x534d4254
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#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
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#define CBMEM_ID_RAM_OOPS 0x05430095
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#define CBMEM_ID_MEMINFO 0x494D454D
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#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
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#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
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#define CBMEM_ID_SPINTABLE 0x59175917
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#define CBMEM_ID_NONE 0x00000000
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#define CBMEM_ID_AGESA_RUNTIME 0x41474553
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#define CBMEM_ID_HOB_POINTER 0x484f4221
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#define CBMEM_ID_TIMESTAMP 0x54494d45
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#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
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#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
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#ifndef __ASSEMBLER__
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#include <stddef.h>
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@ -90,40 +90,40 @@ struct cbmem_id_to_name {
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};
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#define CBMEM_ID_TO_NAME_TABLE \
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{ CBMEM_ID_FREESPACE, "FREE SPACE " }, \
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{ CBMEM_ID_GDT, "GDT " }, \
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{ CBMEM_ID_ACPI, "ACPI " }, \
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{ CBMEM_ID_CBTABLE, "COREBOOT " }, \
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{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
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{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
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{ CBMEM_ID_RESUME, "ACPI RESUME" }, \
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{ CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
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{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
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{ CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
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{ CBMEM_ID_SMBIOS, "SMBIOS " }, \
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{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
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{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
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{ CBMEM_ID_CONSOLE, "CONSOLE " }, \
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{ CBMEM_ID_ELOG, "ELOG " }, \
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{ CBMEM_ID_COVERAGE, "COVERAGE " }, \
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{ CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
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{ CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
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{ CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
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{ CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
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{ CBMEM_ID_ROOT, "CBMEM ROOT " }, \
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{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
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{ CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
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{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
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{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
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{ CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
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{ CBMEM_ID_CBTABLE, "COREBOOT " }, \
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{ CBMEM_ID_CONSOLE, "CONSOLE " }, \
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{ CBMEM_ID_COVERAGE, "COVERAGE " }, \
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{ CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
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{ CBMEM_ID_REFCODE, "REFCODE " }, \
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{ CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
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{ CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
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{ CBMEM_ID_ELOG, "ELOG " }, \
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{ CBMEM_ID_FREESPACE, "FREE SPACE " }, \
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{ CBMEM_ID_GDT, "GDT " }, \
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{ CBMEM_ID_MEMINFO, "MEM INFO " }, \
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{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
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{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
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{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
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{ CBMEM_ID_POWER_STATE, "POWER STATE" }, \
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{ CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
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{ CBMEM_ID_MEMINFO, "MEM INFO " }, \
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{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
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{ CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, \
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{ CBMEM_ID_SPINTABLE, "SPIN TABLE " },
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{ CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
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{ CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
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{ CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
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{ CBMEM_ID_REFCODE, "REFCODE " }, \
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{ CBMEM_ID_RESUME, "ACPI RESUME" }, \
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{ CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
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{ CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
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{ CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
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{ CBMEM_ID_ROOT, "CBMEM ROOT " }, \
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{ CBMEM_ID_SMBIOS, "SMBIOS " }, \
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{ CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
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{ CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
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{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
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{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
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{ CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
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struct cbmem_entry;
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