soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"

Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all
ADL-P and ADL-M Silicon CPUID macros and defines generic name
"Alderlake Platform" as macro value. Also, this will avoid log ADL-M  for
ADL-P CPU and vice-versa. Although currently name field of "cpu_table"
points to only "Alderlake Platform, but it is retained asa placeholder in
future difference platforms.

Please refer EDS doc# 619501 for more details.

The macros are renamed as below:
CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0
CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1
CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2

TEST=Verify boot on Brya. After change, relevent coreboot logs appear as
below:

CPU: ID 906a1, Alderlake Platform, ucode: 00000119
CPU: AES supported, TXT supported, VT supported
MCH: device id 4601 (rev 03) is Alderlake-P
PCH: device id 5181 (rev 00) is Alderlake-P SKU
IGD: device id 46b0 (rev 04) is Alderlake P GT2

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla 2021-06-07 21:28:00 +05:30 committed by Patrick Georgi
parent 0cdcdc736e
commit f93aa04266
3 changed files with 9 additions and 9 deletions

View File

@ -22,9 +22,9 @@ static struct {
u32 cpuid;
const char *name;
} cpu_table[] = {
{ CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
{ CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" },
{ CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" },
{ CPUID_ALDERLAKE_A0, "Alderlake Platform" },
{ CPUID_ALDERLAKE_A1, "Alderlake Platform" },
{ CPUID_ALDERLAKE_A2, "Alderlake Platform" },
};
static struct {

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@ -67,9 +67,9 @@ static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 },
{ X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_B0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 },
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 },
{ 0, 0 },
};

View File

@ -45,9 +45,9 @@
#define CPUID_ELKHARTLAKE_A0 0x90660
#define CPUID_ELKHARTLAKE_B0 0x90661
#define CPUID_ALDERLAKE_S_A0 0x90670
#define CPUID_ALDERLAKE_P_A0 0x906a0
#define CPUID_ALDERLAKE_P_B0 0x906a2
#define CPUID_ALDERLAKE_M_A0 0x906a1
#define CPUID_ALDERLAKE_A0 0x906a0
#define CPUID_ALDERLAKE_A1 0x906a1
#define CPUID_ALDERLAKE_A2 0x906a2
/*
* MP Init callback function to Find CPU Topology. This function is common
* among all SOCs and thus its in Common CPU block.