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mb/intel/leafhill: do LPC/eSPI pad configuration at board-level 

Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.

The soc code gets dropped in CB:49410.

Change-Id: Ie1e53e72c65fdcfe4be2e01134873aa7858c28ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-21 17:09:08 +01:00
parent fccc24f063
commit f9544da6c4
2 changed files with 20 additions and 2 deletions
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6
src/mainboard/intel/leafhill/bootblock.c
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@ -1,9 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <intelblocks/lpc_lib.h> #include <soc/gpio.h>
#include "brd_gpio_early.h"
void bootblock_mainboard_init(void) void bootblock_mainboard_init(void)
{ {
lpc_configure_pads(); gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
} }

16
src/mainboard/intel/leafhill/brd_gpio_early.h Normal file
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@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
/* LPC */
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
};