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mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references 

Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth 2017-06-24 21:45:13 -06:00
parent 1bf55b4070
commit f95911ad37
49 changed files with 98 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/advansus/a785e-i/get_bus_conf.c
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@ -21,7 +21,7 @@
#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
#include <sb_cimx.h>
#endif
@ -128,7 +128,7 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
apicid_sb800 = apicid_base + 0;
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_Late_Post();
#endif
}

4
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);

2
src/mainboard/amd/bettong/BiosCallOuts.c
View File

@ -83,7 +83,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
#endif
/* XHCI configuration */
#if CONFIG_HUDSON_XHCI_ENABLE
#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE)
FchParams_env->Usb.Xhci0Enable = TRUE;
#else
FchParams_env->Usb.Xhci0Enable = FALSE;

4
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -88,7 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/amd/dinar/rd890_cfg.h
View File

@ -28,10 +28,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

8
src/mainboard/amd/dinar/sb700_cfg.h
View File

@ -36,13 +36,13 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif

2
src/mainboard/amd/gardenia/BiosCallOuts.c
View File

@ -97,7 +97,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
#endif
/* XHCI configuration */
#if CONFIG_STONEYRIDGE_XHCI_ENABLE
#if IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)
FchParams_env->Usb.Xhci0Enable = TRUE;
#else
FchParams_env->Usb.Xhci0Enable = FALSE;

20
src/mainboard/amd/inagua/broadcom.c
View File

@ -37,7 +37,7 @@ void broadcom_init(void);
#define be(x) cpu_to_be32(x) //this is used a lot!
/* C forces us to specify these before defining struct selfboot_patch :-( */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
#define INIT1_LENGTH 9
#define INIT2_LENGTH 10
#define INIT3_LENGTH 3
@ -179,7 +179,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
.powerdown.padding = be16(0x0000),
/* Only the lines below may be adapted to your needs ... */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
.header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom
.header.subsys_device = be16(0x1699), //same as pci_device
.header.subsys_vendor = be16(0x14E4), //Broadcom
@ -189,7 +189,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
.header.subsys_vendor = be16(0x121D), //LiPPERT
#endif
.header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
.header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11)
#else
.header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-)
@ -208,7 +208,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
* 1 X 0 | 0x330C5180 - - -
* 1 X 1 | 0x391C6140 - - -
*/
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
.header.basic_config = be16(0x0404), //original for B50610
#else
.header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged
@ -244,7 +244,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
* was added, for reference see Broadcom's changelog.
*/
.init.hunk1_code = {
#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104
be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel)
be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105
@ -258,7 +258,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
.init.hunk2_when = 0x30, //after global reset, PHY reset
.init.hunk2_code = {
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08
be(0x08350001), //v1.06 : PHY15: B50610 slow link fix
be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08
@ -275,20 +275,20 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz
}, //-->INIT3_LENGTH!
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
.init.hunk4_when = 0xD8, //original for B50610
#else
.init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up"
#endif
.init.hunk4_code = {
#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
be(0x083F4300), //CFR-AF: PHY1F: IRQ active high
be(0x083C0000), //CFR-AF: PHY1C: revert driver writes
be(0x08380000), //CFR-AF: PHY18|
be(0x083C0000), //CFR-AF: PHY1C|
#endif
be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode
#else
be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode
@ -300,7 +300,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
.powerdown.hunk1_when = 0x50, //prior to IDDQ MAC
.powerdown.hunk1_code = {
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY
#endif
be(0xF7F30116), // IDDQ PHY

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/amd/parmer/buildOpts.c
View File

@ -154,7 +154,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

2
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -17,7 +17,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

6
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
struct cpuid_result cpuid1;
#endif
@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); /* routing table and start other core0 */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);

2
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -19,7 +19,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>

4
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/amd/thatcher/buildOpts.c
View File

@ -154,7 +154,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

4
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/amd/torpedo/Oem.h
View File

@ -16,7 +16,7 @@
#define BIOS_SIZE 0x04 //04 - 1MB
#endif
#define LEGACY_FREE 0x00
#if !CONFIG_ONBOARD_USB30
#if !IS_ENABLED(CONFIG_ONBOARD_USB30)
#define XHCI_SUPPORT 0x01
#endif

4
src/mainboard/amd/torpedo/platform_cfg.h
View File

@ -294,7 +294,7 @@
#define INCHIP_USB_CINFIG 0x7F
#define INCHIP_USB_OHCI1_CINFIG 0x01
#define INCHIP_USB_OHCI2_CINFIG 0x01
#if CONFIG_ONBOARD_USB30
#if IS_ENABLED(CONFIG_ONBOARD_USB30)
#define INCHIP_USB_OHCI3_CINFIG 0x00
#else
#define INCHIP_USB_OHCI3_CINFIG 0x01
@ -962,7 +962,7 @@
* @li <b>0</b> - Disable
* @li <b>1</b> - Enable
*/
#if CONFIG_ONBOARD_USB30
#if IS_ENABLED(CONFIG_ONBOARD_USB30)
#define SB_XHCI_SWITCH 0
#else
#define SB_XHCI_SWITCH 1

4
src/mainboard/aopen/dxplplusu/romstage.c
View File

@ -65,8 +65,8 @@ void mainboard_romstage_entry(unsigned long bist)
* is lost. Only return addresses from main() and
* scrub_ecc() are recovered to stack via xmm0-xmm3.
*/
#if CONFIG_HW_SCRUBBER
#if !CONFIG_USBDEBUG_IN_ROMSTAGE
#if IS_ENABLED(CONFIG_HW_SCRUBBER)
#if !IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);
e7505_mch_scrub_ecc(ret_addr);
#endif

12
src/mainboard/apple/macbook21/gpio.c
View File

@ -56,7 +56,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
.gpio5 = GPIO_LEVEL_LOW,
#else /* CONFIG_BOARD_APPLE_IMAC52 */
.gpio5 = GPIO_LEVEL_HIGH,
@ -71,7 +72,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio1 = GPIO_INVERT,
.gpio7 = GPIO_INVERT,
#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
.gpio13 = GPIO_INVERT,
#endif
};
@ -80,7 +82,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
#if CONFIG_BOARD_APPLE_IMAC52
#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
.gpio35 = GPIO_MODE_GPIO,
#endif
.gpio38 = GPIO_MODE_GPIO,
@ -89,7 +91,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_mode = {
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
#if CONFIG_BOARD_APPLE_IMAC52
#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
.gpio35 = GPIO_DIR_OUTPUT,
#endif
.gpio38 = GPIO_DIR_OUTPUT,
@ -98,7 +100,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_direction = {
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
#if CONFIG_BOARD_APPLE_IMAC52
#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
.gpio35 = GPIO_LEVEL_LOW,
#endif
.gpio38 = GPIO_LEVEL_HIGH,

3
src/mainboard/apple/macbook21/hda_verb.c
View File

@ -19,7 +19,8 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */
#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21
#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
0x106b2200, /* Subsystem ID */
0x0000000B, /* Number of 4 dword sets */

2
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

2
src/mainboard/asus/a8n_e/romstage.c
View File

@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

2
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

2
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

2
src/mainboard/asus/f2a85-m/acpi/routing.asl
View File

@ -46,7 +46,7 @@
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
#if CONFIG_BOARD_ASUS_F2A85_M_PRO
#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
Package(){0x000FFFFF, 0, INTA, 0 },
Package(){0x000FFFFF, 1, INTB, 0 },
Package(){0x000FFFFF, 2, INTC, 0 },

2
src/mainboard/asus/f2a85-m/buildOpts.c
View File

@ -168,7 +168,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

2
src/mainboard/asus/k8v-x/romstage.c
View File

@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

2
src/mainboard/asus/kcma-d8/bootblock.c
View File

@ -33,7 +33,7 @@ void bootblock_mainboard_init(void)
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);

2
src/mainboard/asus/kfsn4-dre/bootblock.c
View File

@ -62,7 +62,7 @@ void bootblock_mainboard_init(void)
recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
if (recovery_enabled) {
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);

2
src/mainboard/asus/kfsn4-dre_k8/bootblock.c
View File

@ -62,7 +62,7 @@ void bootblock_mainboard_init(void)
recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
if (recovery_enabled) {
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);

2
src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
View File

@ -24,7 +24,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <stdlib.h>

2
src/mainboard/asus/kgpe-d16/bootblock.c
View File

@ -33,7 +33,7 @@ void bootblock_mainboard_init(void)
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
#if CONFIG_USE_OPTION_TABLE
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);

2
src/mainboard/asus/m2n-e/romstage.c
View File

@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/*
* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from

2
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... All core 0 started\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

2
src/mainboard/asus/m2v/romstage.c
View File

@ -238,7 +238,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... All core 0 started\n");
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

4
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

6
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
@ -244,7 +244,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
#if !CONFIG_BOARD_ASUS_M4A785TM
#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM)
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual override */
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {

4
src/mainboard/asus/m5a88-v/get_bus_conf.c
View File

@ -21,7 +21,7 @@
#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
#include <sb_cimx.h>
#endif
@ -128,7 +128,7 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
apicid_sb800 = apicid_base + 0;
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_Late_Post();
#endif
}

4
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);

4
src/mainboard/avalue/eax-785e/get_bus_conf.c
View File

@ -21,7 +21,7 @@
#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
#include <sb_cimx.h>
#endif
@ -128,7 +128,7 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
apicid_sb800 = apicid_base + 0;
#if CONFIG_AMD_SB_CIMX
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_Late_Post();
#endif
}

4
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);

2
src/mainboard/broadcom/blast/mptable.c
View File

@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

2
src/mainboard/broadcom/blast/romstage.c
View File

@ -90,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
wait_all_core0_started();
start_other_cores();

24
src/mainboard/dmp/vortex86ex/romstage.c
View File

@ -72,25 +72,25 @@ void set_ex_powerdown_control(void)
{
u32 powerdown_ctrl;
powerdown_ctrl = pci_read_config32(SB, 0xbc);
#if CONFIG_TEMP_POWERDOWN
#if IS_ENABLED(CONFIG_TEMP_POWERDOWN)
powerdown_ctrl |= (1 << 31);
#endif
#if CONFIG_SATA_POWERDOWN
#if IS_ENABLED(CONFIG_SATA_POWERDOWN)
powerdown_ctrl |= (1 << 30);
#endif
#if CONFIG_ADC_POWERDOWN
#if IS_ENABLED(CONFIG_ADC_POWERDOWN)
powerdown_ctrl |= (1 << 28);
#endif
#if CONFIG_PCIE0_POWERDOWN
#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN)
powerdown_ctrl |= (1 << 13);
#endif
#if CONFIG_MAC_POWERDOWN
#if IS_ENABLED(CONFIG_MAC_POWERDOWN)
powerdown_ctrl |= (1 << 3);
#endif
#if CONFIG_USB1_POWERDOWN
#if IS_ENABLED(CONFIG_USB1_POWERDOWN)
powerdown_ctrl |= (1 << 1);
#endif
#if CONFIG_IDE_POWERDOWN
#if IS_ENABLED(CONFIG_IDE_POWERDOWN)
powerdown_ctrl |= (1 << 0);
#endif
pci_write_config32(SB, 0xbc, powerdown_ctrl);
@ -169,16 +169,16 @@ static void ex_uart_early_init(void)
static void init_wdt1(void)
{
#if CONFIG_WDT1_INITIALIZE
#if CONFIG_WDT1_ENABLE
#if IS_ENABLED(CONFIG_WDT1_INITIALIZE)
#if IS_ENABLED(CONFIG_WDT1_ENABLE)
outb(0x1 << 6, 0xa8);
#endif
u8 wdt1_signal_reg = 0;
#if CONFIG_WDT1_SINGAL_NMI
#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI)
wdt1_signal_reg = 0x0c << 4;
#elif CONFIG_WDT1_SIGNAL_RESET
#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET)
wdt1_signal_reg = 0x0d << 4;
#elif CONFIG_WDT1_SIGNAL_SMI
#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI)
wdt1_signal_reg = 0x0e << 4;
#endif
outb(wdt1_signal_reg, 0xa9);

4
src/mainboard/emulation/qemu-i440fx/northbridge.c
View File

@ -167,7 +167,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
IORESOURCE_ASSIGNED;
}
#if CONFIG_GENERATE_SMBIOS_TABLES
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
static int qemu_get_smbios_data16(int handle, unsigned long *current)
{
struct smbios_type16 *t = (struct smbios_type16 *)*current;
@ -231,7 +231,7 @@ static struct device_operations pci_domain_ops = {
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
#if CONFIG_GENERATE_SMBIOS_TABLES
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
.get_smbios_data = qemu_get_smbios_data,
#endif
};