GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Enable GPIO functions in verstage 

Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.

Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie 2018-10-29 16:48:02 -07:00 committed by Duncan Laurie
parent 51f2f2eba1
commit f95b4a708e
3 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/cannonlake/Makefile.inc
View File

@ -77,11 +77,13 @@ bootblock-y += gpio_cnp_h.c
romstage-y += gpio_cnp_h.c romstage-y += gpio_cnp_h.c
ramstage-y += gpio_cnp_h.c ramstage-y += gpio_cnp_h.c
smm-y += gpio_cnp_h.c smm-y += gpio_cnp_h.c
verstage-y += gpio_cnp_h.c
else else
bootblock-y += gpio.c bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
ramstage-y += gpio.c ramstage-y += gpio.c
smm-y += gpio.c smm-y += gpio.c
verstage-y += gpio.c
endif endif
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake

1
src/soc/intel/common/block/gpio/Makefile.inc
View File

@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c

1
src/soc/intel/common/block/pcr/Makefile.inc
View File

@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c