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nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors 

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Angel Pons 2021-01-20 01:10:48 +01:00 committed by Patrick Georgi
parent ea573b04d8
commit f95b9b4b09
8 changed files with 29 additions and 31 deletions
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9
src/northbridge/intel/haswell/Kconfig
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@ -108,4 +108,13 @@ config ENABLE_DDR_2X_REFRESH
This probably only happens when the DRAM gets hot, but what MRC exactly This probably only happens when the DRAM gets hot, but what MRC exactly
does when this setting is enabled has not been investigated. does when this setting is enabled has not been investigated.
config FIXED_MCHBAR_MMIO_BASE
default 0xfed10000
config FIXED_DMIBAR_MMIO_BASE
default 0xfed18000
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
endif endif

2
src/northbridge/intel/haswell/acpi/ctdp.asl
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@ -9,7 +9,7 @@ Scope (\_SB.PCI0.MCHC)
Name (CTCU, 2) /* CTDP Up Select */ Name (CTCU, 2) /* CTDP Up Select */
Name (SPL1, 0) /* Saved PL1 value */ Name (SPL1, 0) /* Saved PL1 value */
OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE + 0x5000, 0x1000)
Field (MCHB, DWordAcc, Lock, Preserve) Field (MCHB, DWordAcc, Lock, Preserve)
{ {
Offset (0x930), /* PACKAGE_POWER_SKU */ Offset (0x930), /* PACKAGE_POWER_SKU */

6
src/northbridge/intel/haswell/acpi/hostbridge.asl
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@ -175,9 +175,9 @@ Device (PDRC)
Name (PDRS, ResourceTemplate () { Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH

12
src/northbridge/intel/haswell/early_init.c
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@ -14,12 +14,12 @@ static void haswell_setup_bars(void)
{ {
printk(BIOS_DEBUG, "Setting up static northbridge registers..."); printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */ /* Set up all hardcoded northbridge BARs */
pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0);
pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0);
pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */ /* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(HOST_BRIDGE, PAM0, 0x30); pci_write_config8(HOST_BRIDGE, PAM0, 0x30);

15
src/northbridge/intel/haswell/haswell.h
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@ -34,9 +34,8 @@
* MCHBAR * MCHBAR
*/ */
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #include <northbridge/intel/common/fixed_bars.h>
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
@ -62,10 +61,7 @@
* EPBAR - Egress Port Root Complex Register Block * EPBAR - Egress Port Root Complex Register Block
*/ */
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) #define EPBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
#define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x)))
#include "registers/epbar.h" #include "registers/epbar.h"
@ -73,10 +69,7 @@
* DMIBAR * DMIBAR
*/ */
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
#define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x)))
#include "registers/dmibar.h" #include "registers/dmibar.h"

4
src/northbridge/intel/haswell/memmap.h
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@ -3,10 +3,6 @@
#ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__
#define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__
#define DEFAULT_MCHBAR 0xfed10000
#define DEFAULT_DMIBAR 0xfed18000
#define DEFAULT_EPBAR 0xfed19000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_ADDRESS 0xfed90000ULL
#define GFXVT_BASE_SIZE 0x1000 #define GFXVT_BASE_SIZE 0x1000

6
src/northbridge/intel/haswell/northbridge.c
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@ -477,7 +477,7 @@ static void northbridge_topology_init(void)
reg32 &= ~(0xff << 16); reg32 &= ~(0xff << 16);
reg32 |= 1 | (1 << 16); reg32 |= 1 | (1 << 16);
EPBAR32(EPLE1D) = reg32; EPBAR32(EPLE1D) = reg32;
EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; EPBAR64(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
for (unsigned int i = 0; i <= 2; i++) { for (unsigned int i = 0; i <= 2; i++) {
const struct device *const dev = pcidev_on_root(1, i); const struct device *const dev = pcidev_on_root(1, i);
@ -493,7 +493,7 @@ static void northbridge_topology_init(void)
EPBAR32(eple_d[i]) = reg32; EPBAR32(eple_d[i]) = reg32;
pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16));
pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE);
pci_write_config32(dev, PEG_LE1A + 4, 0); pci_write_config32(dev, PEG_LE1A + 4, 0);
pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1);
@ -513,7 +513,7 @@ static void northbridge_topology_init(void)
DMIBAR32(DMILE1D) = reg32; DMIBAR32(DMILE1D) = reg32;
DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; DMIBAR64(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE;
reg32 = DMIBAR32(DMILE2D); reg32 = DMIBAR32(DMILE2D);
reg32 &= ~(0xff << 16); reg32 &= ~(0xff << 16);
reg32 |= 1 | (1 << 16); reg32 |= 1 | (1 << 16);

6
src/northbridge/intel/haswell/romstage.c
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@ -50,9 +50,9 @@ void mainboard_romstage_entry(void)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR, .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = (uintptr_t)DEFAULT_DMIBAR, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = DEFAULT_EPBAR, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,