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superio/nuvoton: Add back Nuvoton NCT6776 support 

Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776),
removing the code as no other mainboard uses it.

The board Intel Saddle Brook uses this device, so add the
code back with minor adaptations.

Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/16519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Teo Boon Tiong 2016-09-05 16:00:07 +08:00 committed by Martin Roth
parent 3674c8240d
commit f95daa510d
6 changed files with 202 additions and 0 deletions
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1
src/superio/nuvoton/Makefile.inc
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@ -19,5 +19,6 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d

3
src/superio/nuvoton/common/early_serial.c
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@ -63,6 +63,9 @@ static void pnp_exit_conf_state(pnp_devfn_t dev)
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
{ {
pnp_enter_conf_state(dev); pnp_enter_conf_state(dev);
if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A))
/* Route GPIO8 pin group to COM A */
pnp_write_config(dev, 0x2a, 0x40);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_iobase(dev, PNP_IDX_IO0, iobase);

23
src/superio/nuvoton/nct6776/Kconfig Normal file
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@ -0,0 +1,23 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
## Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SUPERIO_NUVOTON_NCT6776
bool
select SUPERIO_NUVOTON_COMMON_ROMSTAGE
config SUPERIO_NUVOTON_NCT6776_COM_A
bool
default n

18
src/superio/nuvoton/nct6776/Makefile.inc Normal file
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@ -0,0 +1,18 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
## Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c

58
src/superio/nuvoton/nct6776/nct6776.h Normal file
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@ -0,0 +1,58 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Both NCT6776D and NCT6776F package variants are supported. */
#ifndef SUPERIO_NUVOTON_NCT6776_H
#define SUPERIO_NUVOTON_NCT6776_H
/* Logical Device Numbers (LDN). */
#define NCT6776_FDC 0x00 /* Floppy */
#define NCT6776_PP 0x01 /* Parallel port */
#define NCT6776_SP1 0x02 /* Com1 */
#define NCT6776_SP2 0x03 /* Com2 & IR */
#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */
#define NCT6776_CIR 0x06
#define NCT6776_GPIO6789_V 0x07
#define NCT6776_WDT1_GPIO01A_V 0x08
#define NCT6776_GPIO1234567_V 0x09
#define NCT6776_ACPI 0x0A
#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */
#define NCT6776_VID 0x0D
#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */
#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */
#define NCT6776_SVID 0x14
#define NCT6776_DSLP 0x16 /* Deep sleep */
#define NCT6776_GPIOA_LDN 0x17
/* virtual LDN for GPIO and WDT */
#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V)
#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //?
#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V)
#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V)
#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V)
#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V)
#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V)
#endif /* SUPERIO_NUVOTON_NCT6776_H */

99
src/superio/nuvoton/nct6776/superio.c Normal file
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@ -0,0 +1,99 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
#include <superio/conf_mode.h>
#include "nct6776.h"
/* Both NCT6776D and NCT6776F package variants are supported. */
static void nct6776_init(struct device *dev)
{
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case NCT6776_KBC:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_alt_enable,
.init = nct6776_init,
.ops_pnp_mode = &pnp_conf_mode_8787_aa,
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
{0x0fff, 0}, {0x0fff, 4}, },
{ &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_ACPI},
{ &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
{0x0ffe, 0}, {0x0ffe, 4}, },
{ &ops, NCT6776_VID},
{ &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
{ &ops, NCT6776_GPIO_PP_OD},
{ &ops, NCT6776_SVID},
{ &ops, NCT6776_DSLP},
{ &ops, NCT6776_GPIOA_LDN},
{ &ops, NCT6776_WDT1},
{ &ops, NCT6776_GPIOBASE, PNP_IO0,
{0x0ff8, 0}, },
{ &ops, NCT6776_GPIO0},
{ &ops, NCT6776_GPIO1},
{ &ops, NCT6776_GPIO2},
{ &ops, NCT6776_GPIO3},
{ &ops, NCT6776_GPIO4},
{ &ops, NCT6776_GPIO5},
{ &ops, NCT6776_GPIO6},
{ &ops, NCT6776_GPIO7},
{ &ops, NCT6776_GPIO8},
{ &ops, NCT6776_GPIO9},
{ &ops, NCT6776_GPIOA},
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nuvoton_nct6776_ops = {
CHIP_NAME("NUVOTON NCT6776 Super I/O")
.enable_dev = enable_dev,
};