intel/skylake: ACPI: Clean up formatting in and fix ASL code
Clean up the formatting in various ASL files and remove unused and/or incorrect field definitions. Add back the methods to set the USB power in S3 field in NVS as it is called by the chromium kernel at boot and is currently complaining that the method is not found. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879 Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
83bc0db777
commit
f966d3b3ae
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@ -68,7 +68,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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}
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/* Set flag to enable USB charging in S5 */
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@ -19,32 +19,15 @@
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* Foundation, Inc.
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*/
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// Intel LPC Bus Device - 0:1f.0
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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Name (_DDN, "LPC Bus Device")
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OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
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Field (LPC0, AnyAcc, NoLock, Preserve)
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{
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Offset (0x02),
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PDID, 16, // Device ID
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Offset (0x40),
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PMBS, 16, // PMBASE
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Offset (0x48),
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GPBS, 16, // GPIOBASE
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Offset (0x80), // IO Decode Ranges
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IOD0, 8,
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IOD1, 8,
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}
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Device (DMAC) // DMA Controller
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Device (DMAC)
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{
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Name (_HID, EISAID ("PNP0200"))
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Name (_DDN, "DMA Controller")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x00, 0x00, 0x01, 0x20)
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@ -55,9 +38,10 @@ Device (LPCB)
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})
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}
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Device (FWH) // Firmware Hub
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Device (FWH)
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{
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Name (_HID, EISAID ("INT0800"))
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Name (_DDN, "Firmware Hub")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
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@ -67,28 +51,21 @@ Device (LPCB)
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Device (HPET)
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{
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Name (_HID, EISAID ("PNP0103"))
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Name (BUF0, ResourceTemplate()
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Name (_DDN, "High Precision Event Timer")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
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Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
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})
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Method (_STA, 0) // Device Status
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Method (_STA, 0)
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{
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Return (0xf)
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}
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Method (_CRS, 0, Serialized) // Current resources
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{
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CreateDWordField (BUF0, ^FED0._BAS, HPT0)
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/* TODO: Base address configured need to pass as GNVS */
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Store(HPET_BASE_ADDRESS, HPT0)
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Return(BUF0)
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}
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}
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Device(PIC) // 8259 Interrupt Controller
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Device (PIC)
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{
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Name (_HID, EISAID ("PNP0000"))
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Name (_DDN, "8259 Interrupt Controller")
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x20, 0x20, 0x01, 0x02)
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@ -112,9 +89,10 @@ Device (LPCB)
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})
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}
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Device(MATH) // FPU
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Device (MATH)
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{
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Name (_HID, EISAID ("PNP0C04"))
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Name (_DDN, "Floating Point Unit")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
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@ -122,12 +100,12 @@ Device (LPCB)
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})
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}
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Device(LDRC) // LPC device: Resource consumption
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Device (LDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 2)
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Name (RBUF, ResourceTemplate()
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Name (_DDN, "Legacy Device Resources")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
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IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
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@ -141,27 +119,24 @@ Device (LPCB)
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IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
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0x1, 0xff)
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})
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Method (_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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}
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Device (RTC) // Real Time Clock
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Device (RTC)
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{
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Name (_HID, EISAID ("PNP0B00"))
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Name (_DDN, "Real Time Clock")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x70, 0x70, 1, 8)
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//IRQNoFlags() { 8 }
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})
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}
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Device (TIMR) // Intel 8254 timer
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Device (TIMR)
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{
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Name (_HID, EISAID ("PNP0100"))
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Name (_CRS, ResourceTemplate() {
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Name (_DDN, "8254 Timer")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x40, 0x40, 0x01, 0x04)
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IO (Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags () {0}
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@ -19,11 +19,7 @@
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* Foundation, Inc.
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*/
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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/* PCI Bridge */
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Name (PICP, Package () {
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/* D31: cAVS, SMBus, GbE, Nothpeak */
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Package () { 0x001FFFFF, 0, 0, 16 },
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Package () { 0x001FFFFF, 1, 0, 17 },
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@ -53,7 +49,7 @@ Method(_PRT)
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Package () { 0x0019FFFF, 0, 0, 32 },
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Package () { 0x0019FFFF, 1, 0, 33 },
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Package () { 0x0019FFFF, 2, 0, 34 },
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/* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, 0, 16 },
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Package () { 0x0016FFFF, 1, 0, 17 },
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Package () { 0x0016FFFF, 2, 0, 18 },
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@ -63,24 +59,18 @@ Method(_PRT)
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Package () { 0x0015FFFF, 1, 0, 17 },
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Package () { 0x0015FFFF, 2, 0, 18 },
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Package () { 0x0015FFFF, 3, 0, 19 },
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/* D20: xHCI, OTG,
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* Thermal Subsystem, Camera IO Host Controller
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*/
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/* D20: xHCI, OTG, Thermal, Camera */
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Package () { 0x0014FFFF, 0, 0, 16 },
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Package () { 0x0014FFFF, 1, 0, 17 },
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Package () { 0x0014FFFF, 2, 0, 18 },
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Package () { 0x0014FFFF, 3, 0, 19 },
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/* D19: Integrated Sensor Hub */
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Package () { 0x0013FFFF, 0, 0, 20 },
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/* Host Bridge */
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/* P.E.G. Root Port D1F0 */
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Package () { 0x0001FFFF, 0, 0, 16 },
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Package () { 0x0001FFFF, 1, 0, 17 },
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Package () { 0x0001FFFF, 2, 0, 18 },
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Package () { 0x0001FFFF, 3, 0, 19 },
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/* P.E.G. Root Port D1F1 */
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/* P.E.G. Root Port D1F2 */
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, 0, 16 },
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/* SA Thermal Device */
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@ -90,54 +80,60 @@ Method(_PRT)
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/* SA GMM Device */
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Package () { 0x0008FFFF, 0, 0, 16 },
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})
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} Else {
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Return (Package() {
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/* D31 */
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Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 },
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/* D29 */
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Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 },
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/* D28 */
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Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 },
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/* D27 */
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Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 },
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/* D23 */
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Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 },
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/* D22 */
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Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 },
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/* D20 */
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Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 },
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/* Host bridge */
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Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 },
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/* SA IGFX Device */
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Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 },
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/* SA Thermal Device */
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Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 },
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/* SA Skycam Device */
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Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 },
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/* SA GMM Device */
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Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 },
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})
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}
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}
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Name (PICN, Package () {
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/* D31: cAVS, SMBus, GbE, Nothpeak */
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Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D29: PCI Express Port 9-16 */
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Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D28: PCI Express Port 1-8 */
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Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D27: PCI Express Port 17-20 */
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Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D23 */
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Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D20: xHCI, OTG, Thermal, Camera */
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Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* P.E.G. Root Port D1F0 */
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Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA Skycam Device */
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Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA GMM Device */
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Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
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})
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Method (_PRT)
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{
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If (PICM) {
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Return (^PICP)
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} Else {
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Return (^PICN)
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}
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}
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -24,104 +24,54 @@
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#define BASE_32GB 0x800000000
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#define SIZE_16GB 0x400000000
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Name (_HID, EISAID ("PNP0A08")) // PCIe
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Name (_CID, EISAID ("PNP0A03")) // PCI
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Name (_HID, EISAID ("PNP0A08")) /* PCIe */
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Name (_CID, EISAID ("PNP0A03")) /* PCI */
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Name (_ADR, 0)
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Name (_BBN, 0)
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Device (MCHC)
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{
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Name (_ADR, 0x00000000) // 0:0.0
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Name (_ADR, 0x00000000)
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OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset(0x40), // EPBAR (0:0:0:40)
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EPEN, 1, // Enable
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Offset(0x40), /* EPBAR (0:0:0:40) */
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EPEN, 1, /* Enable */
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, 11,
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EPBR, 20, // EPBAR [31:12]
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EPBR, 20, /* EPBAR [31:12] */
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Offset(0x48), // MCHBAR (0:0:0:48)
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MHEN, 1, // Enable
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Offset(0x48), /* MCHBAR (0:0:0:48) */
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MHEN, 1, /* Enable */
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, 14,
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MHBR, 17, // MCHBAR [31:15]
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MHBR, 17, /* MCHBAR [31:15] */
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Offset(0x54), // DEVEN (0:0:0:54)
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D0EN, 1, // DEV0 Enable
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D1F2, 1, // DEV1 FUN2 Enable
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D1F1, 1, // DEV1 FUN1 Enable
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D1F0, 1, // DEV1 FUN0 Enable
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Offset(0x60), // PCIEXBAR (0:0:0:60)
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PXEN, 1, // Enable
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PXSZ, 2, // PCI Express Size
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Offset(0x60), /* PCIEXBAR (0:0:0:60) */
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PXEN, 1, /* Enable */
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PXSZ, 2, /* PCI Express Size */
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, 23,
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PXBR, 6, // PCI Express BAR [31:26]
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PXBR, 6, /* PCI Express BAR [31:26] */
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Offset(0x68), // DMIBAR (0:0:0:68)
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DIEN, 1, // Enable
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Offset(0x68), /* DMIBAR (0:0:0:68) */
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DIEN, 1, /* Enable */
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, 11,
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DIBR, 20, // DMIBAR [31:12]
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DIBR, 20, /* DMIBAR [31:12] */
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Offset (0x70), // ME Base Address
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Offset (0x70), /* ME Base Address */
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MEBA, 64,
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||||
Offset(0x80), // PAM0 Register (0:0:0:80)
|
||||
PMLK, 1, // PAM Lock bit.
|
||||
, 3,
|
||||
PM0H, 2, // PAM 0, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x81), // PAM1 Register (0:0:0:81)
|
||||
PM1L, 2, // PAM1, Low Nibble
|
||||
, 2,
|
||||
PM1H, 2, // PAM1, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x82), // PAM2 Register (0:0:0:82)
|
||||
PM2L, 2, // PAM2, Low Nibble
|
||||
, 2,
|
||||
PM2H, 2, // PAM2, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x83), // PAM3 Register (0:0:0:83)
|
||||
PM3L, 2, // PAM3, Low Nibble
|
||||
, 2,
|
||||
PM3H, 2, // PAM3, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x84), // PAM4 Register (0:0:0:84)
|
||||
PM4L, 2, // PAM4, Low Nibble
|
||||
, 2,
|
||||
PM4H, 2, // PAM4, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x85), // PAM5 Register (0:0:0:85)
|
||||
PM5L, 2, // PAM5, Low Nibble
|
||||
, 2,
|
||||
PM5H, 2, // PAM5, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset(0x86), // PAM6 Register (0:0:0:86)
|
||||
PM6L, 2, // PAM6, Low Nibble
|
||||
, 2,
|
||||
PM6H, 2, // PAM6, High Nibble
|
||||
, 2,
|
||||
|
||||
Offset (0xa0), // Top of Used Memory
|
||||
Offset (0xa0), /* Top of Used Memory */
|
||||
TOM, 64,
|
||||
|
||||
Offset (0xa8), // Top of Upper Used Memory
|
||||
Offset (0xa8), /* Top of Upper Used Memory */
|
||||
TUUD, 64,
|
||||
|
||||
Offset (0xbc), // Top of Low Used Memory
|
||||
Offset (0xbc), /* Top of Low Used Memory */
|
||||
TLUD, 32,
|
||||
}
|
||||
}
|
||||
|
||||
// Current Resource Settings
|
||||
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
Name (MCRS, ResourceTemplate ()
|
||||
|
|
@ -131,14 +81,16 @@ Method (_CRS, 0, Serialized)
|
|||
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
|
||||
|
||||
/* IO Region 0 */
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
EntireRange,
|
||||
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
|
||||
|
||||
/* PCI Config Space */
|
||||
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
|
||||
|
||||
/* IO Region 1 */
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
EntireRange,
|
||||
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
|
||||
|
||||
/* VGA memory (0xa0000-0xbffff) */
|
||||
|
|
@ -278,13 +230,10 @@ Method (_CRS, 0, Serialized)
|
|||
|
||||
Store (^MCHC.TUUD, Local0)
|
||||
|
||||
If (LLessEqual (Local0, BASE_32GB))
|
||||
{
|
||||
If (LLessEqual (Local0, BASE_32GB)) {
|
||||
Store (BASE_32GB, MMIN)
|
||||
Store (SIZE_16GB, MLEN)
|
||||
}
|
||||
else
|
||||
{
|
||||
} Else {
|
||||
Store (0, MMIN)
|
||||
Store (0, MLEN)
|
||||
}
|
||||
|
|
@ -302,8 +251,7 @@ Name (DM_B, 0) /* to store DMI BAR */
|
|||
/* Get MCH BAR */
|
||||
Method (GMHB, 0, Serialized)
|
||||
{
|
||||
if (LEqual (MH_B,0))
|
||||
{
|
||||
If (LEqual (MH_B, 0)) {
|
||||
ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
|
||||
}
|
||||
Return (MH_B)
|
||||
|
|
@ -312,8 +260,7 @@ Method (GMHB,0,Serialized)
|
|||
/* Get EP BAR */
|
||||
Method (GEPB, 0, Serialized)
|
||||
{
|
||||
if (LEqual (EP_B,0))
|
||||
{
|
||||
If (LEqual (EP_B, 0)) {
|
||||
ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
|
||||
}
|
||||
Return (EP_B)
|
||||
|
|
@ -322,8 +269,7 @@ Method (GEPB,0,Serialized)
|
|||
/* Get PCIe BAR */
|
||||
Method (GPCB, 0, Serialized)
|
||||
{
|
||||
if (LEqual (PC_B,0))
|
||||
{
|
||||
If (LEqual (PC_B, 0)) {
|
||||
ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
|
||||
}
|
||||
Return (PC_B)
|
||||
|
|
@ -332,8 +278,7 @@ Method (GPCB,0,Serialized)
|
|||
/* Get PCIe Length */
|
||||
Method (GPCL, 0, Serialized)
|
||||
{
|
||||
if (LEqual (PC_L,0))
|
||||
{
|
||||
If (LEqual (PC_L, 0)) {
|
||||
ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
|
||||
}
|
||||
Return (PC_L)
|
||||
|
|
@ -342,8 +287,7 @@ Method (GPCL,0,Serialized)
|
|||
/* Get DMI BAR */
|
||||
Method (GDMB, 0, Serialized)
|
||||
{
|
||||
if (LEqual (DM_B,0))
|
||||
{
|
||||
If (LEqual (DM_B, 0)) {
|
||||
ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
|
||||
}
|
||||
Return (DM_B)
|
||||
|
|
@ -398,8 +342,8 @@ Device (PDRC)
|
|||
/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
|
||||
Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
|
||||
|
||||
/* Reserve HPET address decode range */
|
||||
Memory32Fixed (ReadWrite, 0, 0, HPET)
|
||||
/* HPET address decode range */
|
||||
Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
|
||||
|
||||
/* Debug Base Address
|
||||
* Base Address for ACPI debug output memory buffer
|
||||
|
|
@ -407,7 +351,6 @@ Device (PDRC)
|
|||
Memory32Fixed (ReadWrite, 0, 0, DBAD)
|
||||
})
|
||||
|
||||
// Current Resource Settings
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
|
||||
|
|
@ -425,11 +368,6 @@ Device (PDRC)
|
|||
CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
|
||||
Store (\_SB.PCI0.GPCL (), XSZ0)
|
||||
|
||||
CreateDwordField (BUF0, ^HPET._BAS, HBAS)
|
||||
CreateDwordField (BUF0, ^HPET._LEN, HLEN)
|
||||
Store (0xfed00000, HBAS)
|
||||
Store (0x400, HLEN)
|
||||
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue