From f9679c42876bab145f1b7a2a2e6e1eb5331fa418 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 11:53:23 +0100 Subject: [PATCH] nb/intel/gm45: Remove apic 0 from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is added at runtime. Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t400/devicetree.cb | 7 +------ src/mainboard/lenovo/x200/devicetree.cb | 7 +------ src/mainboard/roda/rk9/devicetree.cb | 7 +------ 3 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 7946e34bb2..1df350ab67 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -10,12 +10,7 @@ chip northbridge/intel/gm45 register "slfm" = "1" - device cpu_cluster 0 on - ops gm45_cpu_bus_ops - chip cpu/intel/socket_p - device lapic 0 on end - end - end + device cpu_cluster 0 on ops gm45_cpu_bus_ops end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 814491bacc..6ddd0905a8 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -10,12 +10,7 @@ chip northbridge/intel/gm45 register "slfm" = "1" - device cpu_cluster 0 on - ops gm45_cpu_bus_ops - chip cpu/intel/socket_BGA956 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops gm45_cpu_bus_ops end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index bb2cd70494..e070ae1da6 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -2,12 +2,7 @@ chip northbridge/intel/gm45 # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "slfm" = "1" - device cpu_cluster 0 on - ops gm45_cpu_bus_ops - chip cpu/intel/socket_BGA956 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops gm45_cpu_bus_ops end register "pci_mmio_size" = "2048"