Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size, and correct the numbering on the ram init sequence. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -99,11 +99,6 @@ void main(unsigned long bist)
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enable_smbus();
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smbus_fixup(&ctrl);
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if (bist == 0) {
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print_debug("doing early_mtrr\n");
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early_mtrr_init();
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}
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/* Halt if there was a built-in self test failure. */
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report_bist_failure(bist);
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@ -177,7 +177,7 @@ static void pci_domain_set_resources(device_t dev)
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}
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tomk = rambits * 64 * 1024;
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printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk);
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printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
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/* Compute the Top Of Low Memory (TOLM), in Kb. */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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@ -183,6 +183,8 @@ static void sdram_set_size(const struct mem_controller *ctrl)
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if (result == 0xff)
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die("DRAM module size too big, not supported by CN700\n");
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else
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printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
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pci_write_config8(ctrl->d0f3, 0x40, result);
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pci_write_config8(ctrl->d0f3, 0x48, 0x00);
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@ -400,18 +402,18 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
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read32(rank_address + 0x10);
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/* 3. Mode register set. */
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PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
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PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
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do_ram_command(dev, RAM_COMMAND_MRS);
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read32(rank_address + 0x120000); /* EMRS DLL Enable */
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read32(rank_address + 0x800); /* MRS DLL Reset */
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/* 4. Precharge all again. */
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PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
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PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
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do_ram_command(dev, RAM_COMMAND_PRECHARGE);
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read32(rank_address + 0x0);
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/* 5. Perform 8 refresh cycles. Wait tRC each time. */
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PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
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PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
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do_ram_command(dev, RAM_COMMAND_CBR);
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for (i = 0; i < 8; i++) {
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read32(rank_address + 0x20);
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@ -419,7 +421,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
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}
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/* 6. Mode register set. */
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PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
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PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n");
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/* Safe value for now, BL=8, WR=5, CAS=4 */
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/*
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* (E)MRS values are from the BPG. No direct explanation is given, but
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@ -432,7 +434,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
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read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
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/* 8. Normal operation */
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PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
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PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
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do_ram_command(dev, RAM_COMMAND_NORMAL);
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read32(rank_address + 0x30);
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}
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@ -61,8 +61,10 @@ static void smbus_wait_until_ready(void)
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PRINT_DEBUG("Waiting until SMBus ready\n");
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/* Yes, this is a mess, but it's the easiest way to do it. */
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/* XXX not so messy, but an explanation of the hack would have been better */
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/* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the
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* SMBus Host Status register to go to 0, indicating the operation
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* was completed successfully. I don't remember why I did it this way,
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* but I think it was because ROMCC was running low on registers */
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loops = 0;
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while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
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++loops;
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