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Clarify a comment on an old hack, remove the call to early_mtrr_init 

that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood 2010-08-01 17:20:20 +00:00 committed by Stefan Reinauer
parent bc0f7a68df
commit f97654833a
4 changed files with 12 additions and 13 deletions
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5
src/mainboard/jetway/j7f24/romstage.c
View File

@ -99,11 +99,6 @@ void main(unsigned long bist)
enable_smbus(); enable_smbus();
smbus_fixup(&ctrl); smbus_fixup(&ctrl);
if (bist == 0) {
print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);

2
src/northbridge/via/cn700/northbridge.c
View File

@ -177,7 +177,7 @@ static void pci_domain_set_resources(device_t dev)
} }
tomk = rambits * 64 * 1024; tomk = rambits * 64 * 1024;
printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk); printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
/* Compute the Top Of Low Memory (TOLM), in Kb. */ /* Compute the Top Of Low Memory (TOLM), in Kb. */
tolmk = pci_tolm >> 10; tolmk = pci_tolm >> 10;
if (tolmk >= tomk) { if (tolmk >= tomk) {

12
src/northbridge/via/cn700/raminit.c
View File

@ -183,6 +183,8 @@ static void sdram_set_size(const struct mem_controller *ctrl)
if (result == 0xff) if (result == 0xff)
die("DRAM module size too big, not supported by CN700\n"); die("DRAM module size too big, not supported by CN700\n");
else
printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x40, result);
pci_write_config8(ctrl->d0f3, 0x48, 0x00); pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@ -400,18 +402,18 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
read32(rank_address + 0x10); read32(rank_address + 0x10);
/* 3. Mode register set. */ /* 3. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS); do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x120000); /* EMRS DLL Enable */
read32(rank_address + 0x800); /* MRS DLL Reset */ read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */ /* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE); do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x0); read32(rank_address + 0x0);
/* 5. Perform 8 refresh cycles. Wait tRC each time. */ /* 5. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR); do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
read32(rank_address + 0x20); read32(rank_address + 0x20);
@ -419,7 +421,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
} }
/* 6. Mode register set. */ /* 6. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n");
/* Safe value for now, BL=8, WR=5, CAS=4 */ /* Safe value for now, BL=8, WR=5, CAS=4 */
/* /*
* (E)MRS values are from the BPG. No direct explanation is given, but * (E)MRS values are from the BPG. No direct explanation is given, but
@ -432,7 +434,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */ /* 8. Normal operation */
PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL); do_ram_command(dev, RAM_COMMAND_NORMAL);
read32(rank_address + 0x30); read32(rank_address + 0x30);
} }

6
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
View File

@ -61,8 +61,10 @@ static void smbus_wait_until_ready(void)
PRINT_DEBUG("Waiting until SMBus ready\n"); PRINT_DEBUG("Waiting until SMBus ready\n");
/* Yes, this is a mess, but it's the easiest way to do it. */ /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the
/* XXX not so messy, but an explanation of the hack would have been better */ * SMBus Host Status register to go to 0, indicating the operation
* was completed successfully. I don't remember why I did it this way,
* but I think it was because ROMCC was running low on registers */
loops = 0; loops = 0;
while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
++loops; ++loops;