{nb,soc}: Replace min/max() with MIN/MAX()
Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
836b8d2e45
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f97c1c9d86
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@ -17,6 +17,7 @@
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#include <cf9_reset.h>
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#include <cf9_reset.h>
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#include <device/mmio.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/cache.h>
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#include <delay.h>
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#include <delay.h>
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@ -364,15 +365,15 @@ static void sdram_detect_smallest_params(struct sysinfo *s)
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u32 maxtrtp = 0;
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u32 maxtrtp = 0;
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000);
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maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000);
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maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2);
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maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2);
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maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2);
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maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2);
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maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2);
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maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2);
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maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 +
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maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 +
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(s->dimms[i].spd_data[40] & 0xf));
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(s->dimms[i].spd_data[40] & 0xf));
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maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2);
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maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2);
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maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2);
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maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2);
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maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2);
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maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2);
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}
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}
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/*
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/*
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* TODO: on ddr3 there might be some minimal required values for some
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* TODO: on ddr3 there might be some minimal required values for some
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@ -456,7 +457,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
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// Start with fastest common CAS
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// Start with fastest common CAS
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cas = 0;
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cas = 0;
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highcas = msbp;
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highcas = msbp;
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lowcas = max(lsbp, 5);
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lowcas = MAX(lsbp, 5);
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while (cas == 0 && highcas >= lowcas) {
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while (cas == 0 && highcas >= lowcas) {
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <string.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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@ -1461,7 +1462,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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/* DRAM command ACT */
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/* DRAM command ACT */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4230 + 0x400 * channel) =
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MCHBAR32(0x4230 + 0x400 * channel) =
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(max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
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(MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
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| 4 | (ctrl->tRCD << 16);
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| 4 | (ctrl->tRCD << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);
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MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
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@ -1499,7 +1500,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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/* DRAM command ACT */
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/* DRAM command ACT */
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MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4234 + 0x400 * channel) =
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MCHBAR32(0x4234 + 0x400 * channel) =
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(max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
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(MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
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| 8 | (ctrl->CAS << 16);
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| 8 | (ctrl->CAS << 16);
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MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4214 + 0x400 * channel) = 0x244;
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MCHBAR32(0x4214 + 0x400 * channel) = 0x244;
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@ -1507,7 +1508,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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/* DRAM command RD */
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/* DRAM command RD */
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4238 + 0x400 * channel) =
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MCHBAR32(0x4238 + 0x400 * channel) =
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0x40011f4 | (max(ctrl->tRTP, 8) << 16);
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0x40011f4 | (MAX(ctrl->tRTP, 8) << 16);
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MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
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MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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@ -2101,7 +2102,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
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/* DRAM command ACT */
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/* DRAM command ACT */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4230 + 0x400 * channel) =
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MCHBAR32(0x4230 + 0x400 * channel) =
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((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
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((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
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| 8 | (ctrl->tRCD << 16);
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| 8 | (ctrl->tRCD << 16);
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MCHBAR32(0x4200 + 0x400 * channel) =
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | ctr | 0x60000;
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(slotrank << 24) | ctr | 0x60000;
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@ -2118,7 +2119,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
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/* DRAM command RD */
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/* DRAM command RD */
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4238 + 0x400 * channel) =
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MCHBAR32(0x4238 + 0x400 * channel) =
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0x4001020 | (max(ctrl->tRTP, 8) << 16);
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0x4001020 | (MAX(ctrl->tRTP, 8) << 16);
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MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
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MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
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MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd;
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MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42;
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@ -2662,7 +2663,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4230 + 0x400 * channel) =
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MCHBAR32(0x4230 + 0x400 * channel) =
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0x4 | (ctrl->tRCD << 16) |
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0x4 | (ctrl->tRCD << 16) |
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(max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)
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(MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)
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<< 10);
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<< 10);
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MCHBAR32(0x4200 + 0x400 * channel) =
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | 0x60000;
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(slotrank << 24) | 0x60000;
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@ -2679,7 +2680,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
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/* DRAM command RD */
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/* DRAM command RD */
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4238 + 0x400 * channel) =
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MCHBAR32(0x4238 + 0x400 * channel) =
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0x4005020 | (max(ctrl->tRTP, 8) << 16);
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0x4005020 | (MAX(ctrl->tRTP, 8) << 16);
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MCHBAR32(0x4208 + 0x400 * channel) =
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MCHBAR32(0x4208 + 0x400 * channel) =
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slotrank << 24;
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slotrank << 24;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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@ -2717,9 +2718,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
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rn.end, rn.start + ctrl->edge_offset[i],
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rn.end, rn.start + ctrl->edge_offset[i],
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rn.end - ctrl->edge_offset[i]);
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rn.end - ctrl->edge_offset[i]);
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lower[lane] =
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lower[lane] =
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max(rn.start + ctrl->edge_offset[i], lower[lane]);
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MAX(rn.start + ctrl->edge_offset[i], lower[lane]);
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upper[lane] =
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upper[lane] =
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min(rn.end - ctrl->edge_offset[i], upper[lane]);
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MIN(rn.end - ctrl->edge_offset[i], upper[lane]);
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edges[lane] = (lower[lane] + upper[lane]) / 2;
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edges[lane] = (lower[lane] + upper[lane]) / 2;
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if (rn.all || (lower[lane] > upper[lane])) {
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if (rn.all || (lower[lane] > upper[lane])) {
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printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n",
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printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n",
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@ -2787,7 +2788,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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/* DRAM command ACT */
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/* DRAM command ACT */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
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MCHBAR32(0x4230 + 0x400 * channel) =
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MCHBAR32(0x4230 + 0x400 * channel) =
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(max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
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(MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
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<< 10) | (ctrl->tRCD << 16) | 4;
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<< 10) | (ctrl->tRCD << 16) | 4;
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MCHBAR32(0x4200 + 0x400 * channel) =
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | 0x60000;
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(slotrank << 24) | 0x60000;
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@ -2803,7 +2804,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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/* DRAM command RD */
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/* DRAM command RD */
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
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MCHBAR32(0x4238 + 0x400 * channel) =
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MCHBAR32(0x4238 + 0x400 * channel) =
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0x40011e0 | (max(ctrl->tRTP, 8) << 16);
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0x40011e0 | (MAX(ctrl->tRTP, 8) << 16);
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MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24;
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MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
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@ -2883,10 +2884,10 @@ int discover_timC_write(ramctr_timing *ctrl)
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rn.start + ctrl->timC_offset[i],
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rn.start + ctrl->timC_offset[i],
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rn.end - ctrl->timC_offset[i]);
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rn.end - ctrl->timC_offset[i]);
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lower[channel][slotrank][lane] =
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lower[channel][slotrank][lane] =
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max(rn.start + ctrl->timC_offset[i],
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MAX(rn.start + ctrl->timC_offset[i],
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lower[channel][slotrank][lane]);
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lower[channel][slotrank][lane]);
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upper[channel][slotrank][lane] =
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upper[channel][slotrank][lane] =
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min(rn.end - ctrl->timC_offset[i],
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MIN(rn.end - ctrl->timC_offset[i],
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upper[channel][slotrank][lane]);
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upper[channel][slotrank][lane]);
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}
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}
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@ -2927,7 +2928,7 @@ void normalize_training(ramctr_timing * ctrl)
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int delta;
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int delta;
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mat = 0;
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mat = 0;
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FOR_ALL_LANES mat =
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FOR_ALL_LANES mat =
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max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat);
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MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat);
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printram("normalize %d, %d, %d: mat %d\n",
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printram("normalize %d, %d, %d: mat %d\n",
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channel, slotrank, lane, mat);
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channel, slotrank, lane, mat);
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@ -3080,8 +3081,8 @@ void set_4008c(ramctr_timing * ctrl)
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int max_320c = -10000;
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int max_320c = -10000;
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FOR_ALL_POPULATED_RANKS {
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FOR_ALL_POPULATED_RANKS {
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max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c);
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max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c);
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min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c);
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min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c);
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}
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}
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if (max_320c - min_320c > 51)
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if (max_320c - min_320c > 51)
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@ -13,6 +13,7 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <spi_flash.h>
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#include <spi_flash.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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@ -31,7 +32,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
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static int crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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static int crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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{
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return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len);
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return MIN((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len);
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}
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}
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int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len)
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int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len)
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@ -192,7 +193,7 @@ static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, s
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for (actual = start; actual < len; actual += chunk_len) {
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for (actual = start; actual < len; actual += chunk_len) {
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byte_addr = offset % page_size;
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byte_addr = offset % page_size;
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chunk_len = min(len - actual, page_size - byte_addr);
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chunk_len = MIN(len - actual, page_size - byte_addr);
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chunk_len = crop_chunk(sizeof(cmd), chunk_len);
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chunk_len = crop_chunk(sizeof(cmd), chunk_len);
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cmd[0] = spi_data_ptr->write_cmd;
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cmd[0] = spi_data_ptr->write_cmd;
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@ -14,6 +14,7 @@
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*/
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*/
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#include <device/mmio.h>
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#include <device/mmio.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <fast_spi_def.h>
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#include <fast_spi_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/fast_spi.h>
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@ -157,11 +158,11 @@ static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
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static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr,
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static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr,
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size_t len)
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size_t len)
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{
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{
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size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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size_t xfer_len = MIN(len, SPIBAR_FDATA_FIFO_SIZE);
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size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr;
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size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr;
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if (bytes_left)
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if (bytes_left)
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xfer_len = min(xfer_len, bytes_left);
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xfer_len = MIN(xfer_len, bytes_left);
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return xfer_len;
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return xfer_len;
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}
|
}
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
#include <smbios.h>
|
#include <smbios.h>
|
||||||
#include "smbios.h"
|
#include "smbios.h"
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
|
#include <commonlib/helpers.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <device/dram/ddr3.h>
|
#include <device/dram/ddr3.h>
|
||||||
|
|
||||||
|
@ -63,7 +64,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
|
||||||
|
|
||||||
strncpy((char *)dimm->module_part_number,
|
strncpy((char *)dimm->module_part_number,
|
||||||
module_part_num,
|
module_part_num,
|
||||||
min(sizeof(dimm->module_part_number),
|
MIN(sizeof(dimm->module_part_number),
|
||||||
module_part_number_size));
|
module_part_number_size));
|
||||||
if (module_serial_num)
|
if (module_serial_num)
|
||||||
memcpy(dimm->serial, module_serial_num,
|
memcpy(dimm->serial, module_serial_num,
|
||||||
|
|
|
@ -14,6 +14,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
|
#include <commonlib/helpers.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <delay.h>
|
#include <delay.h>
|
||||||
#include <device/device.h>
|
#include <device/device.h>
|
||||||
|
@ -133,7 +134,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Fill the FIFO with read commands */
|
/* Fill the FIFO with read commands */
|
||||||
fifo_bytes = min(length, 16);
|
fifo_bytes = MIN(length, 16);
|
||||||
bytes_transferred = 0;
|
bytes_transferred = 0;
|
||||||
while (length > 0) {
|
while (length > 0) {
|
||||||
status = regs->ic_raw_intr_stat;
|
status = regs->ic_raw_intr_stat;
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
|
|
||||||
#include <bootstate.h>
|
#include <bootstate.h>
|
||||||
#include <cbmem.h>
|
#include <cbmem.h>
|
||||||
|
#include <commonlib/helpers.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <device/mmio.h>
|
#include <device/mmio.h>
|
||||||
#include <device/pci_ops.h>
|
#include <device/pci_ops.h>
|
||||||
|
@ -156,7 +157,7 @@ static void pch_log_rp_wake_source(void)
|
||||||
{ PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 },
|
{ PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 },
|
||||||
};
|
};
|
||||||
|
|
||||||
maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
|
maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
|
||||||
|
|
||||||
for (i = 0; i < maxports; i++) {
|
for (i = 0; i < maxports; i++) {
|
||||||
dev = pme_status_info[i].dev;
|
dev = pme_status_info[i].dev;
|
||||||
|
|
Loading…
Reference in New Issue