From f98bbda5fb145287c75e944b7c8d91e7c57a672e Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Tue, 7 Apr 2020 16:16:38 -0700 Subject: [PATCH] soc/intel/common: Add method to modify GPIO community PM config This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/common/acpi/gpio.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/soc/intel/common/acpi/gpio.asl diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl new file mode 100644 index 0000000000..364ac73843 --- /dev/null +++ b/src/soc/intel/common/acpi/gpio.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * Configure GPIO Power Management bits + * + * Arg0: GPIO community (0-5) + * Arg1: PM bits in MISCCFG + */ +Method (CGPM, 2, Serialized) +{ + Local0 = GPID (Arg0) + If (Local0 != 0) { + /* Mask off current PM bits */ + PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG) + /* Mask in requested bits */ + PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +}