Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -136,3 +136,103 @@ int acpigen_write_scope(char *name)
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len = acpigen_write_len_f();
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return len + acpigen_emit_stream(name, strlen(name)) + 1;
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}
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int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
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{
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/*
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Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len)
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{
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*/
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char pscope[16];
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int len;
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/* processor op */
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acpigen_emit_byte(0x5b);
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acpigen_emit_byte(0x83);
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len = acpigen_write_len_f();
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sprintf(pscope, "\\._PR_CPU%x", (unsigned int) cpuindex);
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len += acpigen_emit_stream(pscope, strlen(pscope));
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acpigen_emit_byte(cpuindex);
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acpigen_emit_byte(pblock_addr & 0xff);
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acpigen_emit_byte((pblock_addr >> 8) & 0xff);
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acpigen_emit_byte((pblock_addr >> 16) & 0xff);
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acpigen_emit_byte((pblock_addr >> 24) & 0xff);
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acpigen_emit_byte(pblock_len);
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return 6 + 2 + len;
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}
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int acpigen_write_empty_PCT(void)
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{
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/*
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Name (_PCT, Package (0x02)
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{
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ResourceTemplate ()
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{
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Register (FFixedHW,
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0x00, // Bit Width
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0x00, // Bit Offset
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0x0000000000000000, // Address
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,)
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},
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ResourceTemplate ()
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{
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Register (FFixedHW,
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0x00, // Bit Width
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0x00, // Bit Offset
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0x0000000000000000, // Address
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,)
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}
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})
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*/
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static char stream[] = {
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0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */
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0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */
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0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */
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0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */
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0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */
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0x00, 0x79, 0x00
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};
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return acpigen_emit_stream(stream, ARRAY_SIZE(stream));
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}
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/* generates a func with max supported P states */
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int acpigen_write_PPC(u8 nr)
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{
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/*
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Method (_PPC, 0, NotSerialized)
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{
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Return (nr)
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}
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*/
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int len;
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/* method op */
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acpigen_emit_byte(0x14);
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len = acpigen_write_len_f();
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len += acpigen_emit_stream("_PPC", 4);
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/* no fnarg */
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acpigen_emit_byte(0x00);
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/* return */
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acpigen_emit_byte(0xa4);
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/* arg */
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len += acpigen_write_byte(nr);
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acpigen_patch_len(len - 1);
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return len + 3;
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}
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int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
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u32 control, u32 status)
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{
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int len;
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len = acpigen_write_package(6);
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len += acpigen_write_dword(coreFreq);
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len += acpigen_write_dword(power);
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len += acpigen_write_dword(transLat);
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len += acpigen_write_dword(busmLat);
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len += acpigen_write_dword(control);
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len += acpigen_write_dword(status);
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//pkglen without the len opcode
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acpigen_patch_len(len - 1);
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return len;
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}
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@ -34,4 +34,9 @@ int acpigen_write_name(char *name);
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int acpigen_write_name_dword(char *name, uint32_t val);
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int acpigen_write_name_byte(char *name, uint8_t val);
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int acpigen_write_scope(char *name);
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int acpigen_write_PPC(u8 nr);
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int acpigen_write_empty_PCT(void);
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int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
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u32 control, u32 status);
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int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
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#endif
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@ -20,3 +20,4 @@ driver model_fxx_init.o
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object apic_timer.o
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object model_fxx_update_microcode.o
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object processor_name.o
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object powernow_acpi.o
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@ -31,6 +31,7 @@
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#include <../../../southbridge/via/vt8237r/vt8237r.h>
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#include <../../../southbridge/via/k8t890/k8t890.h>
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#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
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#include <cpu/amd/model_fxx_powernow.h>
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extern unsigned char AmlCode[];
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@ -83,7 +84,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
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k8acpi_write_vars();
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/* put PSTATES generator call here */
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amd_model_fxx_generate_powernow(0, 0, 0);
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return (unsigned long) (acpigen_get_current());
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}
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@ -24,14 +24,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
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{
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Include ("amdk8_util.asl")
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/* Define the main processor.*/
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Scope (\_PR)
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{
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Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
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Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
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}
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/* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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