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nb/amd: Fix some white spaces issues 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If8b2db7ff816b9953e9bb767f0f406417e297386
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-07-16 09:47:42 +02:00 committed by Martin L Roth
parent 76c63231d9
commit f9b535eecf
8 changed files with 40 additions and 40 deletions
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16
src/northbridge/amd/agesa/BiosCallOuts.h
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@ -6,18 +6,18 @@
#include <Porting.h>
#include <AGESA.h>
AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_Reset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt);
AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS HeapManagerCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS HeapManagerCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr);
typedef struct {
UINT32 CalloutName;

4
src/northbridge/amd/agesa/agesa_helper.h
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@ -19,8 +19,8 @@ enum {
PICK_CDIT, /* Component Locality Distance Information table */
};
void agesawrapper_setlateinitptr (void *Late);
void *agesawrapper_getlateinitptr (int pick);
void agesawrapper_setlateinitptr(void *Late);
void *agesawrapper_getlateinitptr(int pick);
void amd_initcpuio(void);
void amd_initenv(void);

2
src/northbridge/amd/agesa/dimmSpd.h
View File

@ -4,7 +4,7 @@
#define _DIMMSPD_H_
AGESA_STATUS
AmdMemoryReadSPD (IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
int hudson_readSpd(int spdAddress, char *buf, size_t len);

2
src/northbridge/amd/agesa/family14/state_machine.c
View File

@ -34,7 +34,7 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
struct device *dev = pcidev_on_root(0x18, 2);
#endif
u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
if (mct_cfg_lo & (1<<19)) {
if (mct_cfg_lo & (1 << 19)) {
printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
system_reset();
}

4
src/northbridge/amd/pi/00730F01/acpi_tables.c
View File

@ -9,11 +9,11 @@ unsigned long acpi_fill_madt(unsigned long current)
current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1,
0xFEC20000, 24);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

4
src/northbridge/amd/pi/00730F01/dimmSpd.c
View File

@ -11,7 +11,7 @@
#include <northbridge/amd/pi/dimmSpd.h>
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
@ -37,7 +37,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR
if (spdAddress == 0)
return AGESA_ERROR;
int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128);
if (err)
return AGESA_ERROR;
return AGESA_SUCCESS;

46
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -51,7 +51,7 @@ static unsigned int get_node_nums(void)
if (node_nums)
return node_nums;
node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
node_nums = ((pci_read_config32(get_mc_dev(), 0x60) >> 4) & 7) + 1; //NodeCnt[2:0]
return node_nums;
}
@ -65,7 +65,7 @@ static void get_fx_devs(void)
__f2_dev[i] = get_node_pci(i, 2);
__f4_dev[i] = get_node_pci(i, 4);
if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
fx_devs = i+1;
fx_devs = i + 1;
}
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
@ -123,7 +123,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{
u32 val;
val = 1 | (nodeid<<4) | (linkn<<12);
val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing
* (1)mmio 0xa0000:0xbffff
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df
@ -151,7 +151,7 @@ static void add_fixed_resources(struct device *dev, int index)
resource_t basek, limitk;
if (!get_dram_base_limit(0, &basek, &limitk))
return;
mmio_resource_kb(dev, index++, limitk, 16*1024);
mmio_resource_kb(dev, index++, limitk, 16 * 1024);
}
}
@ -180,7 +180,7 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid)
struct bus *link;
unsigned int sblink;
sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1
sblink = (pci_read_config32(get_mc_dev(), 0x64) >> 8) & 7; // don't forget sublink1
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
@ -189,7 +189,7 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid)
#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
link->secondary, link->subordinate);
/* We need to make sure the vga_pri is under the link */
if ((vga_pri->bus->secondary >= link->secondary) &&
(vga_pri->bus->secondary <= link->subordinate))
@ -220,7 +220,7 @@ static void nb_set_resources(struct device *dev)
static void northbridge_init(struct device *dev)
{
setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1);
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@ -591,7 +591,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
/* IVRS */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
ivrs = (acpi_ivrs_t *) current;
ivrs = (acpi_ivrs_t *)current;
acpi_create_ivrs(ivrs, acpi_fill_ivrs);
current += ivrs->header.length;
acpi_add_table(rsdp, ivrs);
@ -599,10 +599,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current;
srat = (acpi_srat_t *)current;
current += srat->header.length;
acpi_add_table(rsdp, srat);
} else {
@ -612,10 +612,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current;
slit = (acpi_slit_t *)current;
current += slit->header.length;
acpi_add_table(rsdp, slit);
} else {
@ -625,10 +625,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
/* ALIB */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
alib = (acpi_header_t *) current;
alib = (acpi_header_t *)current;
current += alib->length;
acpi_add_table(rsdp, (void *)alib);
}
@ -640,17 +640,17 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
/* SSDT */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
ssdt = (acpi_header_t *)current;
current += ssdt->length;
}
else {
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
}
acpi_add_table(rsdp,ssdt);
acpi_add_table(rsdp, ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
return current;
@ -742,7 +742,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 2) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
}
@ -757,7 +757,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
resource_t base_k, limit_k;
if (!get_dram_base_limit(i, &base_k, &limit_k))
continue; // no memory on this node
if (base_k > 4 *1024 * 1024) break; // don't need to go to check
if (base_k > 4 * 1024 * 1024) break; // don't need to go to check
if (limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G
mem_hole.node_id = i;
@ -822,7 +822,7 @@ static void domain_read_resources(struct device *dev)
i, basek, limitk, sizek);
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
@ -833,13 +833,13 @@ static void domain_read_resources(struct device *dev)
}
basek = mmio_basek;
}
if ((basek + sizek) <= 4*1024*1024) {
if ((basek + sizek) <= 4 * 1024 * 1024) {
sizek = 0;
}
else {
uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
basek = 4 * 1024 * 1024;
sizek = topmem2 / 1024 - basek;
}
}

2
src/northbridge/amd/pi/dimmSpd.h
View File

@ -4,7 +4,7 @@
#define _DIMMSPD_H_
AGESA_STATUS
AmdMemoryReadSPD (IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
int hudson_readSpd(int spdAddress, char *buf, size_t len);