cpu/via/nano: Enable TSC_MONOTONIC_TIMER

Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/via/nano/Kconfig

@@ -24,7 +24,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select UDELAY_TSC
-	select NO_MONOTONIC_TIMER
+	select TSC_MONOTONIC_TIMER
 	select MMX
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS