cpu/via/nano: Enable TSC_MONOTONIC_TIMER
Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -24,7 +24,7 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select UDELAY_TSC
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select UDELAY_TSC
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select NO_MONOTONIC_TIMER
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select TSC_MONOTONIC_TIMER
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select MMX
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select MMX
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select SSE2
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select SUPPORT_CPU_UCODE_IN_CBFS
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