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soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB

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This patch uses index 0x10 for IOE P2SB memory resource allocation
instead of static 0.

Additionally, switches to `mmio_resource` from `mmio_resource_kb`.

TEST=Able to build and boot Google/Rex and observed log as below.

Without the code change:

[SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
            gran 0 limit 0 flags f0000200 index 0

With the code change:

[SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
            gran 0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-10-31 17:35:50 +05:30
parent 770e8e3546
commit f9c075d36d
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/meteorlake/p2sb.c
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@ -35,7 +35,7 @@ void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
static void ioe_p2sb_read_resources(struct device *dev)
{
/* Add the fixed MMIO resource for IOM */
mmio_resource_kb(dev, 0, IOM_BASE_ADDR / KiB, IOM_BASE_SIZE / KiB);
mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE);
}
static void p2sb_read_resources(struct device *dev)