diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index f4a0e0c682..f7bdb2855b 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -116,11 +116,11 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
 		sysinfo->ggc = 0x0002;
 	else {
 		/* 4 for 32MB, default if not set in CMOS */
-		u8 gfxsize = 4;
+		u8 gfxsize = get_int_option("gfx_uma_size", 4);
 
 		/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
 		   2MB GTT + 2MB shadow GTT (0x0b00) else. */
-		get_option(&gfxsize, "gfx_uma_size");
+
 		/* Handle invalid CMOS settings */
 		/* Only allow settings between 32MB and 352MB */
 		gfxsize = MIN(MAX(gfxsize, 4), 12);
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 3c5917b126..b9c944169f 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -149,8 +149,7 @@ static void i945_setup_bars(void)
 	pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
 
 	/* vram size from CMOS option */
-	if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
-		gfxsize = 2;	/* 2 for 8MB */
+	gfxsize = get_int_option("gfx_uma_size", 2);	/* 2 for 8MB */
 	/* make sure no invalid setting is used */
 	if (gfxsize > 6)
 		gfxsize = 2;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index e00026a131..8aa722ccd6 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -707,15 +707,10 @@ static void gma_func0_disable(struct device *dev)
 
 static void gma_func1_init(struct device *dev)
 {
-	u8 val;
-
 	if (!CONFIG(NO_GFX_INIT))
 		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
-	if (get_option(&val, "tft_brightness") == CB_SUCCESS)
-		pci_write_config8(dev, 0xf4, val);
-	else
-		pci_write_config8(dev, 0xf4, 0xff);
+	pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff));
 }
 
 static void gma_generate_ssdt(const struct device *device)
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 4d8fa1328e..8f4aba59da 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3102,10 +3102,7 @@ void chipset_init(const int s3resume)
 	mchbar_write16(0x1170, 0xb880);
 	mchbar_clrsetbits8(0x1210, ~0, 0x84);
 
-	if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
-		/* 0 for 32MB */
-		gfxsize = 0;
-	}
+	gfxsize = get_int_option("gfx_uma_size", 0);	/* 0 for 32MB */
 
 	ggc = 0xb00 | ((gfxsize + 5) << 4);
 
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index a2bbaa0083..df7dcb39e1 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -25,8 +25,7 @@ static void early_graphics_setup(void)
 	pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
 
 	/* Fetch VRAM size from CMOS option */
-	if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS)
-		reg8 = 0;	/* 0 for 8MB */
+	reg8 = get_int_option("gfx_uma_size", 0);	/* 0 for 8MB */
 
 	/* Ensure the setting is valid */
 	if (reg8 > 6)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 922c4b76f6..51b85120c3 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -86,10 +86,9 @@ static void sandybridge_setup_graphics(void)
 
 	printk(BIOS_DEBUG, "Initializing Graphics...\n");
 
-	if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
-		/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
-		gfxsize = 0;
-	}
+	/* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */
+	gfxsize = get_int_option("gfx_uma_size", 0);
+
 	reg16 = pci_read_config16(HOST_BRIDGE, GGC);
 	reg16 &= ~0x00f8;
 	reg16 |= (gfxsize + 1) << 3;
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index de261bda7d..1de9e2868b 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -38,9 +38,8 @@ void x4x_early_init(void)
 		/* Enable internal GFX */
 		pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
 
-		/* Set preallocated IGD size from CMOS */
-		u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
-		get_option(&gfxsize, "gfx_uma_size");
+		/* Set preallocated IGD size from CMOS, or default to 64 MiB */
+		u8 gfxsize = get_int_option("gfx_uma_size", 6);
 		if (gfxsize > 12)
 			gfxsize = 6;
 		/* Need at least 4M for cbmem_top alignment */