mb/google/sarien: Toggle SSD reset pin on DVT2
SSD reset pin had been added on DVT2, the power sequnence requires toggle in boot stage. BUG=b:130741066 TEST=Boot up with simulated DVT2 platform and confirm SSD can be detected during warm reboot. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -211,7 +211,6 @@ static const struct pad_config gpio_table[] = {
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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@ -240,6 +239,8 @@ static const struct pad_config gpio_table[] = {
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/* Early pad configuration in bootblock */
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* SSD RESET pin will stay low first */
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
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/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
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/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
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@ -251,6 +252,7 @@ static const struct pad_config early_gpio_table[] = {
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/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
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/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
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};
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};
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const struct pad_config *variant_gpio_table(size_t *num)
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const struct pad_config *variant_gpio_table(size_t *num)
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@ -197,7 +197,6 @@ static const struct pad_config gpio_table[] = {
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
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/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
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/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
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@ -225,6 +224,7 @@ static const struct pad_config gpio_table[] = {
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/* Early pad configuration in bootblock */
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
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/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
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/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
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@ -236,6 +236,8 @@ static const struct pad_config early_gpio_table[] = {
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/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
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/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
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/* SSD RESET need to stay low first */
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/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
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/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
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/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
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};
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};
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