soc/intel/common/cse_lite: Perform a board specific reset

When CSE Lite jumps from RO to RW, global reset is initiated. When AP is
reset as part of global reset, in some boards TPM initialization fails.
This is because AP reset is not detected by TPM hosting an older firmware
version. To signal TPMs running older firmware version about AP reset, a
modified reset sequence needs to be performed. Hence add support to
perform board-specific reset sequence.

BUG=b:162290856, b:162386991
TEST=Ensure that the device boots to OS with the board-specific reset
sequence when CSE Lite jumps from RO to RW with an older and newer Cr50
firmware.

Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44187
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cse/cse_lite.c

@@ -364,12 +364,21 @@ static bool cse_set_next_boot_partition(enum boot_partition_id bp)
 	return true;
 }
 
+__weak void cse_board_reset(void)
+{
+	/* Default weak implementation, does nothing. */
+}
+
 /* Set the CSE's next boot partition and issues system reset */
 static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp)
 {
 	if (!cse_set_next_boot_partition(bp))
 		return false;
 
+	/* Allow the board to perform a reset for CSE RO<->RW jump */
+	cse_board_reset();
+
+	/* If board does not perform the reset, then perform global_reset */
 	do_global_reset();
 
 	die("cse_lite: Failed to reset the system\n");

src/soc/intel/common/block/include/intelblocks/cse.h

@@ -219,4 +219,8 @@ uint8_t cse_wait_com_soft_temp_disable(void);
  * currently selected partition.
  */
 void cse_fw_sync(void *unused);
+
+/* Perform a board-specific reset sequence for CSE RO<->RW jump */
+void cse_board_reset(void);
+
 #endif // SOC_INTEL_COMMON_CSE_H