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Intel cpus: apply some good programming practices in new CAR 

Delete dead CAR code and whitespace fixes.

Replace cryptic 32bit hex values with existing LAPIC definitions.

Do not assume state of direction flag before "rep" instruction.

Do not load immediate values on temporary registers when not needed.

Parameter pushed on stack was not popped (or flushed) after returning
from call. This is a sort-of memory leak if multiple call's are
implemented the same way.

Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/643
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Kyösti Mälkki 2012-02-28 01:45:44 +02:00 committed by Patrick Georgi
parent 325b92f64a
commit f9d1a42d98
1 changed files with 15 additions and 24 deletions
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37
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -21,6 +21,10 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cpu/x86/lapic_def.h>
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#define CPU_MAXPHYADDR 36 #define CPU_MAXPHYADDR 36
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
@ -38,9 +42,9 @@ cache_as_ram:
post_code(0x20) post_code(0x20)
/* Send INIT IPI to all excluding ourself. */ /* Send INIT IPI to all excluding ourself. */
movl $0x000C4500, %eax movl LAPIC(ICR), %edi
movl $0xFEE00300, %esi movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
movl %eax, (%esi) movl %eax, (%edi)
/* Zero out all fixed range and variable range MTRRs. */ /* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi movl $mtrr_table, %esi
@ -92,11 +96,10 @@ clear_mtrrs:
movl %eax, %cr0 movl %eax, %cr0
/* Clear the cache memory reagion. */ /* Clear the cache memory reagion. */
movl $CACHE_AS_RAM_BASE, %esi cld
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
rep stosl rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
@ -131,11 +134,10 @@ clear_mtrrs:
/* Set up the stack pointer. */ /* Set up the stack pointer. */
#if CONFIG_USBDEBUG #if CONFIG_USBDEBUG
/* Leave some space for the struct ehci_debug_info. */ /* Leave some space for the struct ehci_debug_info. */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp
#else #else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp
#endif #endif
movl %eax, %esp
/* Restore the BIST result. */ /* Restore the BIST result. */
movl %ebp, %eax movl %ebp, %eax
@ -146,6 +148,7 @@ clear_mtrrs:
/* Call romstage.c main function. */ /* Call romstage.c main function. */
call main call main
addl $4, %esp
post_code(0x2f) post_code(0x2f)
@ -167,18 +170,6 @@ clear_mtrrs:
post_code(0x31) post_code(0x31)
invd invd
#if 0
xorl %eax, %eax
xorl %edx, %edx
movl $MTRRphysBase_MSR(0), %ecx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
wrmsr
movl $MTRRphysBase_MSR(1), %ecx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
wrmsr
#endif
post_code(0x33) post_code(0x33)
@ -196,7 +187,7 @@ clear_mtrrs:
post_code(0x38) post_code(0x38)
/* Enable Write Back and Speculative Reads for the first 1MB. */ /* Enable Write Back and Speculative Reads for low RAM. */
movl $MTRRphysBase_MSR(0), %ecx movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx xorl %edx, %edx