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src/southbridge: Add required space before the open parenthesis 

Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26035
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-05-03 17:21:02 +02:00 committed by Martin Roth
parent c4c2d4ec7a
commit f9de5a4b43
9 changed files with 9 additions and 9 deletions
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2
src/southbridge/amd/sr5650/early_setup.c
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@ -104,7 +104,7 @@ static u8 get_nb_rev(device_t nb_dev)
{ {
u8 reg; u8 reg;
reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */ reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */
switch(reg & 3) switch (reg & 3)
{ {
case 0x00: case 0x00:
reg = REV_SR5650_A11; reg = REV_SR5650_A11;

2
src/southbridge/broadcom/bcm5785/lpc.c
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@ -84,7 +84,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
base = res->base; base = res->base;
end = resource_end(res); end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) { switch (base) {
case 0x60: //KBC case 0x60: //KBC
case 0x64: case 0x64:
reg |= (1<<29); break; reg |= (1<<29); break;

2
src/southbridge/intel/bd82x6x/me_8.x.c
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@ -864,7 +864,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr; p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
switch(mbp_item_id) { switch (mbp_item_id) {
case 0x101: case 0x101:
SET_UP_COPY(fw_version_name); SET_UP_COPY(fw_version_name);

2
src/southbridge/intel/fsp_bd82x6x/me_8.x.c
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@ -861,7 +861,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr; p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
switch(mbp_item_id) { switch (mbp_item_id) {
case 0x101: case 0x101:
SET_UP_COPY(fw_version_name); SET_UP_COPY(fw_version_name);

2
src/southbridge/intel/fsp_i89xx/me_8.x.c
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@ -816,7 +816,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr; p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
switch(mbp_item_id) { switch (mbp_item_id) {
case 0x101: case 0x101:
SET_UP_COPY(fw_version_name); SET_UP_COPY(fw_version_name);

2
src/southbridge/intel/lynxpoint/me_9.x.c
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@ -1016,7 +1016,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
for (i = 0; i < mbp->header.mbp_size - 1;) { for (i = 0; i < mbp->header.mbp_size - 1;) {
mbp_item_header *item = (void *)&mbp->data[i]; mbp_item_header *item = (void *)&mbp->data[i];
switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) { switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
case MBP_IDENT(KERNEL, FW_VER): case MBP_IDENT(KERNEL, FW_VER):
ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);

2
src/southbridge/nvidia/mcp55/lpc.c
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@ -197,7 +197,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
base = res->base; base = res->base;
end = resource_end(res); end = resource_end(res);
printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) { switch (base) {
case 0x3f8: /* COM1 */ case 0x3f8: /* COM1 */
reg |= (1 << 0); reg |= (1 << 0);
break; break;

2
src/southbridge/sis/sis966/lpc.c
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@ -203,7 +203,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
base = res->base; base = res->base;
end = resource_end(res); end = resource_end(res);
printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) { switch (base) {
case 0x3f8: // COM1 case 0x3f8: // COM1
reg |= (1<<0); break; reg |= (1<<0); break;
case 0x2f8: // COM2 case 0x2f8: // COM2

2
src/southbridge/sis/sis966/sis966.c
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@ -80,7 +80,7 @@ void sis966_enable(device_t dev)
} }
devfn = (dev->path.pci.devfn) & ~7; devfn = (dev->path.pci.devfn) & ~7;
switch(deviceid) { switch (deviceid) {
case PCI_DEVICE_ID_SIS_SIS966_USB: case PCI_DEVICE_ID_SIS_SIS966_USB:
devfn -= (1<<3); devfn -= (1<<3);
index = 8; index = 8;