mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN. Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -6,8 +6,10 @@ config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select HAVE_ACPI_TABLES
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select MAINBOARD_USES_FSP2_0
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select IPMI_KCS
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select MAINBOARD_USES_FSP2_0
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select OCP_DMI
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select PARALLEL_MP_AP_WORK
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select SOC_INTEL_SKYLAKE_SP
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select SUPERIO_ASPEED_AST2400
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@ -1,7 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-y += ramstage.c ipmi.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <drivers/ipmi/ipmi_kcs.h>
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#include "ipmi.h"
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void ipmi_set_ppin(struct ppin_req *req)
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{
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int ret;
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struct ipmi_rsp rsp;
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ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN,
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(const unsigned char *) req, sizeof(*req),
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(unsigned char *) &rsp, sizeof(rsp));
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if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) {
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printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
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__func__, ret, rsp.completion_code);
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return;
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}
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printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n");
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}
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef TIOGAPASS_IPMI_H
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#define TIOGAPASS_IPMI_H
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#include <types.h>
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#define IPMI_NETFN_OEM 0x30
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#define IPMI_OEM_SET_PPIN 0x77
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/* PPIN for 2 CPU IPMI request */
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struct ppin_req {
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uint32_t cpu0_lo;
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uint32_t cpu0_hi;
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uint32_t cpu1_lo;
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uint32_t cpu1_hi;
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} __packed;
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/* Send CPU0 and CPU1 PPIN to BMC */
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void ipmi_set_ppin(struct ppin_req *req);
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#endif
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@ -1,9 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <soc/ramstage.h>
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#include <bootstate.h>
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#include <drivers/ipmi/ipmi_ops.h>
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#include <drivers/ocp/dmi/ocp_dmi.h>
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#include <gpio.h>
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#include <soc/ramstage.h>
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#include <soc/lewisburg_pch_gpio_defs.h>
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#include "ipmi.h"
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extern struct fru_info_str fru_strings;
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void mainboard_silicon_init_params(FSPS_UPD *params)
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{
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}
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@ -14,4 +22,42 @@ static void pull_post_complete_pin(void *unused)
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gpio_output(GPP_B20, 0);
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}
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static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t)
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{
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/* OEM string 1 to 6 */
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ocp_oem_smbios_strings(dev, t);
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/* OEM string 7 */
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if (fru_strings.board_info.custom_count > 1 &&
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*(fru_strings.board_info.board_custom + 1) != NULL)
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t->count = smbios_add_oem_string(t->eos,
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*(fru_strings.board_info.board_custom + 1));
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else
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t->count = smbios_add_oem_string(t->eos, TBF);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->get_smbios_strings = tp_oem_smbios_strings,
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read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings);
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}
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static void mainboard_final(void *chip_info)
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{
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struct ppin_req req;
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req.cpu0_lo = xeon_sp_ppin[0].lo;
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req.cpu0_hi = xeon_sp_ppin[0].hi;
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req.cpu1_lo = xeon_sp_ppin[1].lo;
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req.cpu1_hi = xeon_sp_ppin[1].hi;
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/* Set PPIN to BMC */
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ipmi_set_ppin(&req);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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.final = mainboard_final,
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};
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);
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