soc/intel/cannonlake: Plumb TetonGlacierMode into dt

The following plumbs through the enabling of Intel's TetonGlacierMode
allows for reconfiguring the PCIe lanes at runtime for hybrid drives
to be accessable via devicetree.

BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.

Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/cannonlake/chip.h

@@ -242,6 +242,9 @@ struct soc_intel_cannonlake_config {
 	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
 	uint8_t HeciEnabled;
 
+	/* Enables support for Teton Glacier hybrid storage device */
+	uint8_t TetonGlacierMode;
+
 	/* PL1 Override value in Watts */
 	uint32_t tdp_pl1_override;
 	/* PL2 Override value in Watts */

src/soc/intel/cannonlake/fsp_params.c

@@ -374,6 +374,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 #endif
 	params->Device4Enable = config->Device4Enable;
 
+	/* Teton Glacier hybrid storage support */
+	params->TetonGlacierMode = config->TetonGlacierMode;
+
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */