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northbridge/intel/haswell: Fix undefined behavior 

Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.

Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Ryan Salsamendi 2017-06-30 17:29:37 -07:00 committed by Nico Huber
parent 889ce9c91e
commit fa0725dead
3 changed files with 13 additions and 7 deletions
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4
src/drivers/intel/gma/i915_reg.h
View File

@ -2979,7 +2979,7 @@
/* Ironlake */
#define CPU_VGACNTRL 0x41000
#define CPU_VGA_DISABLE (1<<31)
#define CPU_VGA_DISABLE (1UL<<31)
#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
@ -4177,7 +4177,7 @@
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
#define HSW_PWR_WELL_ENABLE (1<<31)
#define HSW_PWR_WELL_ENABLE (1UL<<31)
#define HSW_PWR_WELL_STATE (1<<30)
#define HSW_PWR_WELL_CTL5 0x45410
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)

4
src/northbridge/intel/haswell/gma.c
View File

@ -252,13 +252,13 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */
gtt_poll(0x138124, (1 << 31), (0 << 31));
gtt_poll(0x138124, (1UL << 31), (0UL << 31));
/* Mailbox Data - RC6 VIDS */
gtt_write(0x138128, 0x00000000);
/* Mailbox Command */
gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */
gtt_poll(0x138124, (1 << 31), (0 << 31));
gtt_poll(0x138124, (1UL << 31), (0UL << 31));
/* Enable PM Interrupts */
gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |

12
src/northbridge/intel/haswell/northbridge.c
View File

@ -36,6 +36,7 @@
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;
u32 mask;
*base = 0;
*len = 0;
@ -47,15 +48,20 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
*base = pciexbar_reg & mask;
*len = 256 * 1024 * 1024;
return 1;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27);
*base = pciexbar_reg & mask;
*len = 128 * 1024 * 1024;
return 1;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27) | (1 << 26);
*base = pciexbar_reg & mask;
*len = 64 * 1024 * 1024;
return 1;
}