mb/google/guybrush: use gpio.h include

Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-12-06 21:10:53 +01:00
parent 0a7a2694f9
commit fa0bf5c2a4
14 changed files with 10 additions and 12 deletions

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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <amdblocks/gpio.h>
#include <amdblocks/smi.h> #include <amdblocks/smi.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/smi.h> #include <soc/smi.h>
#include <variant/ec.h> #include <variant/ec.h>

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@ -3,8 +3,8 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <gpio.h>
#include <soc/platform_descriptors.h> #include <soc/platform_descriptors.h>
#include <soc/gpio.h>
#include <types.h> #include <types.h>
/* All PCIe Resets are handled in coreboot */ /* All PCIe Resets are handled in coreboot */

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@ -4,7 +4,6 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h>
/* GPIO configuration in ramstage */ /* GPIO configuration in ramstage */
/* Please make sure that *ALL* GPIOs are configured in this table */ /* Please make sure that *ALL* GPIOs are configured in this table */

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@ -2,7 +2,7 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <device/device.h> #include <device/device.h>
#include <soc/gpio.h> #include <gpio.h>
bool __weak variant_has_pcie_wwan(void) bool __weak variant_has_pcie_wwan(void)
{ {

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@ -6,6 +6,7 @@
#include <ec/ec.h> #include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h> #include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h> #include <baseboard/gpio.h>
/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
#include <soc/gpio.h> #include <soc/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \ #define MAINBOARD_EC_SCI_EVENTS \

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@ -3,6 +3,7 @@
#ifndef __BASEBOARD_GPIO_H__ #ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__
/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
#include <soc/gpio.h> #include <soc/gpio.h>
/* SPI Write protect */ /* SPI Write protect */

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@ -3,7 +3,7 @@
#ifndef __BASEBOARD_VARIANTS_H__ #ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__
#include <amdblocks/gpio.h> #include <gpio.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <platform_descriptors.h> #include <platform_descriptors.h>

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@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <boardid.h> #include <boardid.h>
#include <gpio.h>
#include <security/tpm/tis.h> #include <security/tpm/tis.h>
#include <soc/gpio.h>
int tis_plat_irq_status(void) int tis_plat_irq_status(void)
{ {

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@ -3,7 +3,6 @@
#include <baseboard/gpio.h> #include <baseboard/gpio.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h>
/* This table is used by guybrush variant */ /* This table is used by guybrush variant */
static const struct soc_amd_gpio override_ramstage_gpio_table[] = { static const struct soc_amd_gpio override_ramstage_gpio_table[] = {

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@ -4,7 +4,6 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <boardid.h> #include <boardid.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h>
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {

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@ -3,8 +3,8 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <boardid.h> #include <boardid.h>
#include <device/device.h> #include <device/device.h>
#include <soc/gpio.h>
#include <amdblocks/cpu.h> #include <amdblocks/cpu.h>
#include <gpio.h>
bool variant_has_pcie_wwan(void) bool variant_has_pcie_wwan(void)
{ {

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@ -4,7 +4,6 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <boardid.h> #include <boardid.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h>
/* This table is used by nipperkin variant with board version < 2. */ /* This table is used by nipperkin variant with board version < 2. */
static const struct soc_amd_gpio bid1_override_gpio_table[] = { static const struct soc_amd_gpio bid1_override_gpio_table[] = {

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@ -5,7 +5,7 @@
#include <device/device.h> #include <device/device.h>
#include <drivers/i2c/tpm/chip.h> #include <drivers/i2c/tpm/chip.h>
#include <drivers/uart/acpi/chip.h> #include <drivers/uart/acpi/chip.h>
#include <soc/gpio.h> #include <gpio.h>
static void cr50_devtree_update(void) static void cr50_devtree_update(void)
{ {

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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/gpio.h>
#include <arch/io.h> #include <arch/io.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h>
#include <psp_verstage.h> #include <psp_verstage.h>
#include <security/vboot/vboot_common.h> #include <security/vboot/vboot_common.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>